Experimental verification of timing measurement circuit with self-calibration

Abstract

This paper describes the architecture, implementation and measurement results for a Time-to-Digital Converter (TDC), with histogram-method self-calibration, for high-speed I/O interface circuit test applications. We have implemented the proposed TDC using a Programmable Systemon-Chip (PSoC), and measurement results show that TDC linearity is improved by the self-calibration. All TDC circuits, as well as the self-calibration circuits can be implemented as digital circuits, even by using FPGA instead of full custom ICs, so this is ideal for fine CMOS implementation with short design time.

A Glitch-Free Time-to-Digital Converter Architecture Based on Gray Code

“…The architecture of a basic flash-type TDC is shown in Fig.1 (1)- (4) . The flash-type TDC uses a delay line which consists of CMOS inverter buffer delays and D flip-flops (DFF).…”

A Residue Number System Based Time-to-Digital Converter Architecture and its FPGA Implementation

“…The TDC will play an increasingly important role in the nano-CMOS era, because it is well suited to implementation with fine digital CMOS processes. [1][2][3][4][5].…”