Exploiting programmable bist for the diagnosis of embedded memory cores

Appello, D.; Bernardi, Paolo; Fudoli, A.; Rebaudengo, Maurizio; Reorda, Matteo Sonza; Tancorre, V.; Violante, M.

doi:10.1109/test.2003.1270861

Cited by 31 publications

(15 citation statements)

References 19 publications

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“…We have implemented the NPMBIST with the same March 2 algorithm, 16K × 16 memory size and 0.13 µm technology library for fair comparison with previous PMBISTs in Table 3. The PMBIST in [2] and [3] only support March al- Table 3 Comparison with previous PMBIST. gorithms and requires many instruction bits when implementing March 2 algorithm.…”

Section: Npmbist Implementation and Resultsmentioning

confidence: 87%

An Effective Programmable Memory BIST for Embedded Memory

Park

Han

et al. 2009

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper proposes a micro-code based Programmable Memory BIST (PMBIST) architecture that can support various kinds of test algorithms. The proposed Non-linear PMBIST (NPMBIST) guarantees high flexibility and high fault coverage using not only March algorithms but also non-linear algorithms such as Walking and Galloping. This NPMBIST has an optimized hardware overhead, since algorithms can be implemented with the minimum bits by the optimized instructions. Finally, various and complex algorithms can be run thanks to its support of multi-loop.

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Section: Npmbist Implementation and Resultsmentioning

confidence: 87%

An Effective Programmable Memory BIST for Embedded Memory

Park

Han

et al. 2009

IEICE Trans. Inf. & Syst.

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“…The programmable controllers required about 4x to 5x the area of a static BIST controller based on MARCH algorithms. Microcode-based controllers have also been proposed by Jakobsen et al [JDP+01], Appello et al [ABF+03]. A CPU-based controller uses an on-chip special-purpose processor for the generation of test sequences; such controllers are proposed in [ZS+03].…”

Section: Previous Workmentioning

confidence: 99%

Layout-Aware and Programmable Memory BIST Synthesis for Nanoscale System-on-Chip Designs

Kokrady

Ravikumar

Chandrachoodan

2008

2008 17th Asian Test Symposium

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Debugging memory test failures in a system-on-chip design is becoming difficult due to the growing number and sizes of the embedded memories. Low-complexity marching tests, which are ideally suited for production testing, are insufficient for debug and diagnostics. On-chip support for multiple memory test algorithms can be prohibitively expensive. Moreover, memory test engineers would like the flexibility to make small changes to the test sequence. Runtime programmability can be provided through the use of programmable finite state machines and/or microcode in the BIST controllers. Since such controllers have higher area requirement, it is difficult to employ multiple controllers and distribute them geographically on the chip. Therefore, the BIST controller can become a routing hot-spot. Existing memory BIST insertion flows operate on a post-synthesis net-list and ignore the constraints that will be posed by the physical design step that will follow. These constraints include routing congestion and interconnect timing. Similarly, the synthesis of the BIST logic must also address area, test application time and test power constraints. In this paper, we formulate the problem of programmable memory BIST synthesis as an optimization problem and describe an implementation. Results show upto 3X improvement in area and wirelength for industrial designs when a layout-aware flow is used as opposed to manual BIST implementation.

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“…A custom March-based programmable BIST [3] able to execute a test program for SRAM cores has been used to validate the proposed methodology.…”

Section: Experimental Set-upmentioning

confidence: 99%

“…From the hardware point of view, it is based on the integration of a lowoverhead programmable Built-In Self-Test (BIST) module equipped with diagnosis oriented features [3] for static RAMs, accessible through an IEEE 1500 interface. The diagnosis flow requires an interactive sequence of March Tests [4] executions.…”

Section: Introductionmentioning

confidence: 99%

Embedded Memory Diagnosis: An Industrial Workflow

Appello

Tancorre

Bernardi

et al. 2006

2006 IEEE International Test Conference

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Embedded memory modules are sensitive components that deeply influence production yield of integrated devices. For fast yield improvement, an efficient manufacturing test must supply advanced defect characterization that helps in discovering technology weaknesses and finding strategies for improvement. This paper presents an industrial workflow for embedded memory diagnosis. It is based on the integration of March-based diagnostic BIST hardware in an IEEE 1500-compliant environment, and on a novel diagnostic algorithm for determining the fault model associated to the retrieved syndromes. An experimental implementation showing the feasibility of the approach is presented.

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Exploiting programmable bist for the diagnosis of embedded memory cores

Cited by 31 publications

References 19 publications

An Effective Programmable Memory BIST for Embedded Memory

An Effective Programmable Memory BIST for Embedded Memory

Layout-Aware and Programmable Memory BIST Synthesis for Nanoscale System-on-Chip Designs

Embedded Memory Diagnosis: An Industrial Workflow

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