Exploiting the Potential of Computation Reuse Through Approximate Computing

He, Xin; Jiang, Shuhao; Lu, Wangtao; Yan, Guihai; Li, Xiaowei

doi:10.1109/tmscs.2016.2617343

Cited by 17 publications

(9 citation statements)

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“…Notations are defined in Figure 4(b). Our accelerator composes of a simple controller and a dedicated memory named a dataset table (DST) 6 to store limited sets of previous input data and corresponding results of the computations of a target hotspot. In this figure, "target function or loop" is a target hotspot (function or loop in most cases) to be accelerated in an application.…”

Section: Overview Goalmentioning

confidence: 99%

“…These techniques are well suited for relatively small, simple systems like DSP circuits [7,13,20]. Contrarily, the coarse-grained techniques aim at reducing the amount of computations, such as task skipping [17,18], input sampling [22], pruning [25], and data reuse [6,14,15], and they are more suitable for relatively large, complex systems, like multicore processors with multiple memory hierarchies [5,6,14,15,17,22,25].…”

Section: Introductionmentioning

confidence: 99%

“…More specifically, we focus on "data reuse," which has been mainly utilized to resolve cache miss penalties [15,18], cache footprint reduction [14], or synchronization penalties [17] in multicore processors, but has been rarely utilized for computational reuse particularly in single-core processors. Among existing works in AC, References [5,6,23] proposed the most relevant approaches in computation-reuse architectures, but they presume that processors have rich memories and resources, which cannot be expected in embedded systems. Moreover, they have two issues in the flexibility and scalability; Because the reusable approximate data are statically pre-set in a lookup-table based on a profile, they cannot flexibly take into account the run-time changes of input data.…”

Section: Introductionmentioning

confidence: 99%

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Approximate Data Reuse-based Accelerator Design for Embedded Processor

Osawa

Hara-Azumi

2019

ACM Trans. Des. Autom. Electron. Syst.

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Due to increasing diversity and complexity of applications in embedded systems, accelerator designs tradingoff area/energy-efficiency and design-productivity are becoming a further crucial issue. Targeting applications in the category of Recognition, Mining, and Synthesis (RMS), this study proposes a novel accelerator design to achieve a good trade-off in efficiency and design-productivity (or reusability) by introducing a new computing paradigm called "approximate computing" (AC). Leveraging from the facts that frequently executed parts of applications (i.e., hotspots) are conventionally the target of acceleration and that RMS applications are error-tolerant and often take similar input data repeatedly, our proposed accelerator reuses previous computational results of similar enough data to reduce computations. The proposed accelerator is composed of a simple controller and a dedicated memory to store limited sets of previous input data with corresponding computational results in a hotspot. Therefore, this accelerator can be applied to different and/or multiple hotspots/applications only through small extension of the controller, to achieve efficient accelerator design and resolve the design-productivity issue. We conducted quantitative evaluations using a representative RMS application (image compression) to demonstrate the effectiveness of our method over conventional ones with precise computing. Moreover, we provide important findings on parameter exploration for our accelerator design, offering a wider applicability of our accelerator to other applications. CCS Concepts: • Computer systems organization → Embedded hardware;

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Section: Overview Goalmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Approximate Data Reuse-based Accelerator Design for Embedded Processor

Osawa

Hara-Azumi

2019

ACM Trans. Des. Autom. Electron. Syst.

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“…Computational reuse and value prediction are techniques that cash the inputs and results of previous computation execution to predict a current instant [14]. In conjunction with approximate computing [15], computation reuse proved effective at reducing the processing of CNNs by mapping the inputs' similarities and identifying avoidable computations.…”

Section: Introductionmentioning

confidence: 99%

SLID: Exploiting Spatial Locality in Input Data as a Computational Reuse Method for Efficient CNN

et al. 2021

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Convolutional Neural Networks (CNNs) revolutionized computer vision and reached the state-of-the-art performance for image processing, object recognition, and video classification. Even though CNN inference is notoriously compute-intensive, as convolutions account for > 90% of the total operation tasks, the ability to tradeoff between accuracy, performance, power, and latency to meet target application makes it an open research topic. This paper proposes the Spatial Locality Input Data (SLID) method for computational reuse during the inference stage for a pre-trained network. The method exploits input data spatial locality via skipping partial processing of the multiply-and-accumulate (MAC) operations for adjacent data and equating its value to previously computed ones. SLID improves the throughput of resource-constrained devices (Internet-of-Things, edge devices) and accelerates computations during the inference phase by reducing the number of MAC operations. Such approximate computing schema does not require a similarity quantification step nor any modification for the training stage. The computational data reuse was evaluated on three well-known distinctive CNN structures and data sets with alternating layer selections: LeNet, CIFAR-10, and AlexNet. The computational data reuse method saves up to 34.9%, 49.84%, and 31.5% of MAC operations while reducing the accuracy by 8%, 3.7%, and 5.0% for the three models mentioned earlier, respectively. Besides, the proposed method saves on memory access by eliminating data fetching of skipped inputs. Furthermore, filter size, strides, and padding on the accuracy and savings of operations are analyzed. SLID is the first work to exploit the input spatial locality for savings on CNN convolution operations with minimal accuracy loss and without memory or computational overhead. This makes it a great option to support intelligence at the edge.

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“…at the architecture, circuit, and device levels. Customized NN accelerators aim at higher energy efficiency, approximate circuits trade accuracy for energy efficiency [5,6], and emerging technologies (e.g. RRAM crossbar) perform low power NN computation in memory [7].…”

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confidence: 99%

AxTrain

Liu

et al. 2018

Proceedings of the International Symposium on Low Power Electronics and Design

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The intrinsic error tolerance of neural network (NN) makes approximate computing a promising technique to improve the energy efficiency of NN inference. Conventional approximate computing focuses on balancing the efficiency-accuracy trade-off for existing pre-trained networks, which can lead to suboptimal solutions. In this paper, we propose AxTrain, a hardware-oriented training framework to facilitate approximate computing for NN inference. Specifically, AxTrain leverages the synergy between two orthogonal methods-one actively searches for a network parameters distribution with high error tolerance, and the other passively learns resilient weights by numerically incorporating the noise distributions of the approximate hardware in the forward pass during the training phase. Experimental results from various datasets with near-threshold computing and approximation multiplication strategies demonstrate AxTrain's ability to obtain resilient neural network parameters and system energy efficiency improvement. INTRODUCTIONAn Artificial Neural Network (ANN) is a biologically inspired machine learning model that has been practically demonstrated to deliver superior performance in many recognition, mining, and synthesis (RMS) applications [1]. The success of ANN can be attributed to innovations across the computing system stack: To achieve higher accuracy, deeper and more complex networks are created along with more advanced training algorithms. To speed up NN training and deployment, powerful parallel computing engines (e.g., GPUs) are designed to accelerate computationally intensive mathematical operations. Despite the improved performance, energy efficiency still remains a limiting factor when deploying advanced ANNs into edge devices with stringent power budgets.A growing body of research has been proposed to tackle energy efficiency from diverse perspectives. Algorithmically, the focus is to simplify neural network (NN) by either using more concise network models (e.g. ResNet [2] and binary neural networks [3]) or pruning and compressing existing models [4]. From the hardware perspective, efficiency-driven optimizations have been conducted Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org.

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Exploiting the Potential of Computation Reuse Through Approximate Computing

Cited by 17 publications

References 50 publications

Approximate Data Reuse-based Accelerator Design for Embedded Processor

Approximate Data Reuse-based Accelerator Design for Embedded Processor

SLID: Exploiting Spatial Locality in Input Data as a Computational Reuse Method for Efficient CNN

AxTrain

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