Exploring performance, power, and temperature characteristics of 3D systems with on-chip DRAM

Abstract

3D integration enables stacking DRAM layers on processor cores within the same chip. On-chip memory has the potential to dramatically improve performance due to lower memory access latency and higher bandwidth. Higher core performance increases power density, requiring a thorough evaluation of the tradeoff between performance and temperature. This paper presents a comprehensive framework for exploring the power, performance, and temperature characteristics of 3D systems with on-chip DRAM. Utilizing this framework, we quantify the performance improvement as well as the power and thermal profiles of parallel workloads running on a 16-core 3D system with on-chip DRAM. The 3D system improves application performance by 72.6% on average in comparison to an equivalent 2D chip with off-chip memory. Power consumption per core increases by up to 32.7%. The increase in peak chip temperature, however, is limited to 1.5 o C as the lower power DRAM layers share the heat of the hotter cores. Experimental results show that while DRAM stacking is a promising technique for high-end systems, efficient thermal management strategies are needed in embedded systems with cost or space restrictions to compensate for the lack of efficient cooling.

Memory-Aware Scheduling for Fixed Priority Hard Real-Time Computing Systems

“…In this work, we consider a 3D system architecture, similar to that in [192], consisting of a logic layer with multiple DRAM layers on top of it. We assume face-to-back bonding and inter-layer communication using through-silicon vias (TSVs) that are etched through the bulk silicon for vertically connecting the layers [150].…”