Express Cube Topologies for on-Chip Interconnects

Grot, Boris; Hestness, Joel; Keckler, Stephen W.; Mutlu, Onur

doi:10.1109/hpca.2009.4798251

Cited by 163 publications

(116 citation statements)

References 25 publications

Supporting

Mentioning

110

Contrasting

Order By: Relevance

“…High radix routers [18], [19] usually have higher serialization delay, and do not work well under adversarial traffic [12]. NoC with multi-hop traversal in single cycle capability such as SMART [12] shows significant latency reduction.…”

Section: Related Workmentioning

confidence: 99%

An Efficient 2D Router Architecture for Extending the Performance of Inhomogeneous 3D NoC-Based Multi-Core Architectures

Agyeman

Zong

2016

2016 International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW)

View full text Add to dashboard Cite

Abstract-To meet the performance and scalability demands of the fast-paced technological growth towards exascale and BigData processing with the performance bottleneck of conventional metal based interconnects, alternative interconnect fabrics such as inhomogeneous three dimensional integrated Network-onChip (3D NoC) has emanated as a cost-effective solution for emerging multi-core design. However, these interconnects tradeoff optimized performance for cost by restricting the number of area and power hungry 3D routers. Consequently, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in inhomogeneous 3D NoCs. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in the network to reduce the average packet latency under various traffic loads. Simulation shows that, the proposed router can reduce the average packet delay by an average of 45% in 3D NoCs.

show abstract

Section: Related Workmentioning

confidence: 99%

An Efficient 2D Router Architecture for Extending the Performance of Inhomogeneous 3D NoC-Based Multi-Core Architectures

Agyeman

Zong

2016

2016 International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW)

View full text Add to dashboard Cite

show abstract

“…MECS [Grot et al, 2009] [Balfour and Dally, 2006] and bus-like one-tomany channels. The bus-like one-to-may channel is similar in architecture as a bus, but only the master node can send data to one or many slave nodes connected to the channel.…”

Section: Mixed Architectures Hybrid Interconnectmentioning

confidence: 99%

“…The duo [Jin et al, 2012] hybrid interconnect consists of a baseline 2D-mesh NoC augmented with a bus-like reconfigurable multidrop channels (the same in the MECS [Grot et al, 2009] hybrid interconnect). Due to the reconfiguration ability, each row or each column has only one channel instead of 2(n − 1) in MECS.…”

mentioning

confidence: 99%

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Pham‐Quoc¹,

Heisswolf²,

Werner³

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

View full text Add to dashboard Cite

Heterogeneous multicore systems are becoming increasingly important as the need for computation power grows, especially when we are entering into the big data era. As one of the main trends in heterogeneous multicore, hardware accelerator systems provide application specific hardware circuits and are thus more energy efficient and have higher performance than general purpose processors, while still providing a large degree of flexibility. However, system performance dose not scale when increasing the number of processing cores due to the communication overhead which increases greatly with the increasing number of cores. Although data communication is a primary anticipated bottleneck for system performance, the interconnect design for data communication among the accelerator kernels has not been well addressed in hardware accelerator systems. A simple bus or shared memory is usually used for data communication between the accelerator kernels. In this dissertation, we address the issue of interconnect design for heterogeneous hardware accelerator systems.Evidently, there are dependencies among computations, since data produced by one kernel may be needed by another kernel. Data communication patterns can be specific for each application and could lead to different types of interconnect. In this dissertation, we use detailed data communication profiling to design an optimized hybrid interconnect that provides the most appropriate support for the communication pattern inside an application while keeping the hardware resource usage for the interconnect minimal. Firstly, we propose a heuristicbased approach that takes application data communication profiling into account to design a hardware accelerator system with a custom interconnect. A number of solutions are considered including crossbar-based shared local memory, direct memory access (DMA) supporting parallel processing, local buffers, and hardware duplication. This approach is mainly useful for embedded system where the hardware resources are limited. Secondly, we propose an automated hybrid interconnect design using data communication profiling to define an optimized interconnect for accelerator kernels of a generic hardware accelerator system. The hybrid interconnect consists of a network-on-chip (NoC), vii viii ABSTRACT shared local memory, or both. To minimize hardware resource usage for the hybrid interconnect, we also propose an adaptive mapping algorithm to connect the computing kernels and their local memories to the proposed hybrid interconnect. Thirdly, we propose a hardware accelerator architecture to support streaming image processing. In all presented approaches, we implement the approach using a number of benchmarks on relevant reconfigurable platforms to show their effectiveness. The experimental results show that our approaches not only improve system performance but also reduce overall energy consumption compared to the baseline systems.

show abstract

“…With the increasing complexity and die sizes of DSP and multimedia ICs, such designs need to be heavily pipelined, making our technique more suitable with each process generation. Recent Network-on-Chip (NOC) topologies such as the flattened butterfly [1] and Multidrop Excess Channels [2] (MECS) could benefit from our approach as well.…”

Section: Introductionmentioning

confidence: 99%

On-chip bidirectional wiring for heavily pipelined systems using network coding

Bollapalli

Garg

Gulati

et al. 2009

2009 IEEE International Conference on Computer Design

View full text Add to dashboard Cite

Abstract-In this paper, we describe a low-area, reducedpower on-chip point-to-point bidirectional communication scheme for heavily pipelined systems. When data needs to be transmitted bidirectionally between two on-chip locations, the traditional approach resorts to either using two unidirectional wires, or to using a single wire (with a unidirectional transfer at any given time instant). In contrast, our bidirectional communication scheme allows data to be transmitted simultaneously between two on-chip locations, with a single wire performing the bidirectional data transfer. Our approach borrows ideas from the emerging area of network coding (in the field of communication). By utilizing coding units (which also serve the purpose of buffering the signals) along the wire between the two endpoints, we are able to achieve the same throughput as a traditional approach, while reducing the total area utilization by about 49.8% (thereby reducing routing congestion), and the total power consumption by about 11.5%. The area and power results include the contribution of routing wires, coding units, drivers, the clock distribution network and the required reset wire. Our bidirectional communication approach is ideally suited for heavily pipelined data intensive systems.

show abstract

Express Cube Topologies for on-Chip Interconnects

Cited by 163 publications

References 25 publications

An Efficient 2D Router Architecture for Extending the Performance of Inhomogeneous 3D NoC-Based Multi-Core Architectures

An Efficient 2D Router Architecture for Extending the Performance of Inhomogeneous 3D NoC-Based Multi-Core Architectures

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

On-chip bidirectional wiring for heavily pipelined systems using network coding

Contact Info

Product

Resources

About