Extended Cyclostatic Dataflow Program Compilation and Execution for an Integrated Manycore Processor

Aubry, Pascal; Beaucamps, Pierre-Edouard; Blanc, Frédéric; Bodin, Bruno; Carpov, Sergiu; Cudennec, Loïc; David, Vincent; Dore, Philippe; Dubrulle, Paul; Dinechin, Benoît Dupont de; Galea, François; Goubier, Thierry; Harrand, Michel; Jones, Samuel; Lesage, Jean-Denis; Louise, Stéphane; Chaisemartin, Nicolas Morey; Nguyễn, Thanh Hải; Raynaud, Xavier; Sirdey, Renaud

doi:10.1016/j.procs.2013.05.330

Cited by 34 publications

(23 citation statements)

References 15 publications

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“…More generally, our work is also closely related to previous work on the design of NoCs with support for real-time and safety-critical applications [20], [21], [22], [23] and on application mapping onto many-core architectures [24], [25], [26], [27], [28], the difference being given by the integrated approach we use and by the statically scheduled NoC communications which ensure high timing precision and efficiency for the chosen class of applications.…”

Section: Related Workmentioning

confidence: 88%

Reconciling performance and predictability on a many-core through off-line mapping

Carle

Djemal

Genius

et al. 2014

2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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Abstract-We start from a general-purpose many-core architecture designed for average-case performance and ease of use. In particular, its distributed shared memory programming model allows the use of a code generation flow based on the (unmodified) gcc compiler chain. We modify this architecture and extend the code generation flow to allow the construction of efficient hard real-time systems starting from dependent task specifications. We rely on a static (off-line) real-time scheduling paradigm welladapted to embedded control and signal processing applications with regular control structure.We modify the architecture (and in particular the on-chip network) to allow the implementation of static schedules with very high (clock cycle) temporal precision. On the software side, we define application mapping rules ensuring that the timing precision provided by the hardware is not lost. These mapping rules include requirements on the allocation of data variables to specific RAM banks and on the use of locks to ensure the absence of contentions during access to shared resources. Applications complying with these rules can be written manually or automatically obtained using a new mapping tool that takes all the allocation and scheduling decisions. Compilation of the resulting C code is still done using the (unmodified) gcc compiler chain. The resulting platform provides good performance, and at the same provides very high timing precision, as shown by two case studies (an embedded controller and an implementation of the FFT).We conclude our paper with a presentation of some ongoing work on the subject: A case study (an implementation of the H.264 decoder) meant to test the limitations of our method.

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Section: Related Workmentioning

confidence: 88%

Reconciling performance and predictability on a many-core through off-line mapping

Carle

Djemal

Genius

et al. 2014

2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

View full text Add to dashboard Cite

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“…Here one has to consider two cases: (1) Such effects are absent in so called timing composable platforms that are commonly considered for deploying of real-time systems, e. g. the Multi-Purpose Processor Array of Kalray [5]. In addition they might be avoidable by code modification techniques 5 ; (2) Allowing the bounds on the number of cache misses and worst-case execution times of phases to originate from different program execution paths, breaks up the dependency between worst-case execution time and number of memory accesses, at the cost of tightness.…”

Section: Discussionmentioning

confidence: 99%

A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets

et al. 2014

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A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets. Real-time systemshttp://dx.doi.org/10.1007/s11241-014-9211-y Access to the published version may require subscription. N.B. When citing this work, cite the original published paper. Abstract Multicore technology has the potential for drastically increasing productivity of embedded real-time computing. However, joint use of hardware, e.g., caches, memory banks and on-chip buses makes the integration of multiple real-time applications into a single system difficult: resource accesses are exclusive and need to be sequenced. Moreover, resource access schemes of modern off-the-shelf multicore chips are commonly optimized for the average-case, rather than being timing predictable. Real-time analysis for such architectures is complex, as execution times depend on the deployed hardware, as well as on the software executing on other cores. This will ask for significant abstractions in the timing analysis, where the resulting pessimism will lead to over-provisioned system designs and a lowered productivity as the number of applications to be put together into a single architecture needs to be decreased. In response to this, (a) we present a formal approach for bounding the worst-case response time of concurrently executing real-time tasks under resource contention and almost arbitrarily complex resource arbitration policies, with a focus on main memory as shared resource, (b) we present a simulation framework which allows for detailed modeling and empirical evaluation of modern multicore platforms and applications running on top of them, and (c) we present experiments to demonstrate the advantages and disadvantages of the presented methodologies and compare their accuracy. For limiting non-determinism inherent to the occurrence of cache misses, we particularly take advantage from the PRedictable Execution Model (PREM) as discussed in recent works.

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“…However, our objective is to use TPDF to implement streaming applications on many-core platforms with highly parallel schedules such as the MPPA-256 [1] clustered architecture, from Kalray, comprising 256 cores. The native dataflow programming model developed in ΣC (Sigma-C) for MPPA-256 uses the notion of canonical period [9], which represents the partial order corresponding to the execution of one iteration of the application in the form of a graph whose vertices are, for each task a i , the q i first occurrences of this task and channels are dependencies between these occurrences.…”

Section: Schedulingmentioning

confidence: 99%

Transaction Parameterized Dataflow: A Model for Context-Dependent Streaming Applications

Khanh

Louise

Cohen

2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-Static dataflow programming models are well suited to the development of embedded many-core systems. However, complex signal and media processing applications often display dynamic behavior that do not fit the classical static restrictions. We propose Transaction Parameterized Dataflow (TPDF), a new model of computation combining integer parameters-to express dynamic rates-and a new type of control actor-to allow topology changes and time constraints enforcement. We present static analyses for liveness and bounded memory usage. We also introduce a static scheduling heuristic to map TPDF to massively parallel embedded platforms. We validate the model and associated methods using a cognitive radio application, demonstrating significant buffer size and performance improvements compared to state of the art models including Cyclo-Static Dataflow (CSDF).

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Extended Cyclostatic Dataflow Program Compilation and Execution for an Integrated Manycore Processor

Cited by 34 publications

References 15 publications

Reconciling performance and predictability on a many-core through off-line mapping

Reconciling performance and predictability on a many-core through off-line mapping

A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets

Transaction Parameterized Dataflow: A Model for Context-Dependent Streaming Applications

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