Extension of Coulomb blockade region by quantum confinement in the ultrasmall silicon dot in a single-hole transistor at room temperature

Abstract

First room-temperature (RT) observation of extended Coulomb blockade (CB) region due to quantum confinement in the ultrasmall silicon dot in a single-hole transistor (SHT) is described. We fabricate single-dot SHTs in the form of metal-oxide-semiconductor field-effect transistors with an extremely constricted channel. Both large CB oscillation with the peak-to-valley current ratio (PVCR) of 40.4 and clear negative differential conductance (NDC) with the PVCR of 11.8 (highest ever reported) are observed at RT in the fabricated device. The observed NDC is attributable to the resonant tunneling due to the large quantum level spacing in the ultrasmall dot whose size is estimated to be about 2 nm.

Si-based ultrasmall multiswitching single-electron transistor operating at room-temperature

“…1 However, the reliability of room-temperature ͑RT͒ operation and requirement of complementary metal-oxide-semiconductor-compatible processes have been the main bottlenecks for implementing further practical device applications. Significant earlier work has been aimed at implementing a RT-operating SET, using various schemes, device structures, and fabrication processes, [2][3][4][5][6][7] but reliable processes for the controlled fabrication of ultrasmall size Coulomb islands of less than 5 nm have not been firmly established yet, limiting practical device applications at RT.…”

Single-electron and quantum confinement limits in length-scaled silicon nanowires

“…at corners where the NW meets source / drain regions, to enhance oxidation and create SiO 2 tunnel barriers. Both single [17] and chains of islands [24], forming a multiple tunnel junction (MTJ), have been used.…”

“…Relatively recently, by reducing the Si island size to < 10 nm, such that the single-electron charging energy E c >> k B T = 26 meV at 300 K, strong room-temperature single-electron current oscillations with very large peak -valley ratios have been reported [17,24,29,32].…”

“…Unlike 'classical' FETs, these devices inherently show performance improvements with reduction in size, but may require new approaches both for operation within circuits, and for lithographic and fabrication technologies at the sub-5 nm scale [14]. As highly scaled Si nanowire (SiNW) can be used as the basis for SE / QD transistors operating at room temperature [15][16][17], it is possible to envisage a direct transition from SiNW FETs to SE / QD devices. Si NWs may then inherently provide the basis for a quantum effect 'beyond CMOS' technology [14].…”

One electron-controlled multiple-valued dynamic random-access-memory

“…[1][2][3][4][5][6][7] Considerable efforts toward room-temperature operation have recently been demonstrated by ultrasmall dot-based SET structures. [8][9][10][11][12][13] Particularly, most recent works [11][12][13] reported the implementation of CMOS-compatible sub_5nm Si SET whose charge stability features three and a half clear multiple Coulomb diamonds at 300K, showing high peak-to-valley current ratio (PVCR). However, despite such aggressive downscaling silicon nanotechnology, the conventional state-of-the-art dynamic random-access-memory (DRAM) has been keeping the binary scheme, and this makes further increasing storage functionality difficult in the future terabit device applications.…”