Electrical operation of room-temperature (RT) single dopant atom quantum dot (QD) transistors, based on phosphorous atoms isolated within nanoscale SiO2 tunnel barriers, is presented. In contrast to single dopant transistors in silicon, where the QD potential well is shallow and device operation limited to cryogenic temperature, here, a deep (~2 eV) potential well allows electron confinement at RT. Our transistors use ~10 nm size scale Si/SiO2/Si pointcontact tunnel junctions, defined by scanning probe lithography and geometric oxidation.'Coulomb diamond' charge stability plots are measured at 290 K, with QD addition energy ~0.3 eV. Theoretical simulation gives a QD size of similar order to the phosphorous atom separation ~2 nm. Extraction of energy states predicts an anharmonic QD potential, fitted using a Morse oscillator-like potential. The results extend single-atom transistor operation to RT, enable tunnelling spectroscopy of impurity atoms in insulators, and allow the energy landscape for P atoms in SiO2 to be determined.

Single nanometre scale quantum dots (QDs) have significant potential for many 'beyond CMOS' nanoelectronics and quantum computation applications. The fabrication and measurement of few nanometre silicon point-contact QD single-electron transistors are reported, which both operate at room temperature (RT) and are fabricated using standard processes. By combining thin silicon-on-insulator wafers, specific device geometry, and controlled oxidation, <10 nm nanoscale point-contact channels are defined. In this limit of the point-contact approach, ultra-small, few nanometre scale QDs are formed, enabling RT measurement of the full QD characteristics, including excited states to be made. A remarkably large QD electron addition energy ∼0.8 eV, and a quantum confinement energy ∼0.3 eV, are observed, implying a QD only ∼1.6 nm in size. In measurements of 19 RT devices, the extracted QD radius lies within a narrow band, from 0.8 to 2.35 nm, emphasising the single-nanometre scale of the QDs. These results demonstrate that with careful control, 'beyond CMOS' RT QD transistors can be produced using current 'conventional' semiconductor device fabrication techniques.

Single-electron devices operating at room temperature require sub-5 nm quantum dots having tunnel junctions of comparable dimensions. Further development in nanoelectronics depends on the capability to generate mesoscopic structures and interfacing these with complementary metal–oxide–semiconductor devices in a single system. The authors employ a combination of two novel methods of fabricating room temperature silicon single-electron transistors (SETs), Fowler–Nordheim scanning probe lithography (F-N SPL) with active cantilevers and cryogenic reactive ion etching followed by pattern-dependent oxidation. The F-N SPL employs a low energy electron exposure of 5–10 nm thick high-resolution molecular resist (Calixarene) resulting in single nanodigit lithographic performance [Rangelow et al., Proc. SPIE 7637, 76370V (2010)]. The followed step of pattern transfer into silicon becomes very challenging because of the extremely low resist thickness, which limits the etching depth. The authors developed a computer simulation code to simulate the reactive ion etching at cryogenic temperatures (−120 °C). In this article, the authors present the alliance of all these technologies used for the manufacturing of SETs capable to operate at room temperatures.

Quantum-effects will play an important role in both future CMOS and 'beyond CMOS' technologies. By comparing single-electron transistors formed in unpatterned, uniform-width silicon nanowire devices with core widths from ~5 -40 nm, and gated lengths of 1 µm and ~50 nm, we show conditions under which these effects become significant. Coulomb blockade drain-source current-voltage characteristics, and single-electron current oscillations with gate voltage have been observed at room temperature. Detailed electrical characteristics have been measured from 8 -300 K.We show that while shortening the nanowire gate length to 50 nm reduces the likelihood of quantum dots to only a few, it increases their influence on the electrical characteristics. This highlights explicitly both the significance of quantum effects for understanding the electrical performance of nominally 'classical' SiNW devices and also their potential for new quantum effect 'beyond CMOS' devices. a) Electronic mail: z.durrani@imperial.ac.uk 2

Suspended silicon nanowires have significant potential for a broad spectrum of device applications. A suspended p-type Si nanowire incorporating Si nanocrystal quantum dots has been used to form a single-hole transistor. Transistor fabrication uses a novel and rapid process, based on focused gallium ion beam exposure and anisotropic wet etching, generating &lt;10 nm nanocrystals inside suspended Si nanowires. Electrical characteristics at 10 K show Coulomb diamonds with charging energy ∼27 meV, associated with a single dominant nanocrystal. Resonant tunnelling features with energy spacing ∼10 meV are observed, parallel to both diamond edges. These may be associated either with excited states or hole–acoustic phonon interactions, in the nanocrystal. In the latter case, the energy spacing corresponds well with reported Raman spectroscopy results and phonon spectra calculations.