2019
DOI: 10.4028/www.scientific.net/msf.963.105
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Extensive 99% Killer Defect Free 4H-SiC Epitaxial Layer toward High Current Large Chip Devices

Abstract: Epitaxial growth of 4H-SiC on 150 mm wafers using 3 x 150 mm multi-wafer CVD has been investigated to realize extremely low defect density on the epitaxial layer in order to achieve stable fabrication of high current devices with large die size. By optimizing the epitaxial growth conditions as well as the improved procedures for the inside the furnace to remain cleaned stably for cumulative growth processes, we have demonstrated an extensive 99% defect free epitaxial inlayer in a 5 mm x 5 mm block evaluation w… Show more

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Cited by 8 publications
(3 citation statements)
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“…As previously reported [6], we have already established very low surface defects in the drift layer with the buffer layer under conventional growth conditions. In this study, we verified the improved growth conditions of the REB layer does not impair the surface quality of the drift layer because it is considered that the surface quality of the buffer layer may affect the quality of the drift layer.…”
Section: Realization Of Low Surface Defect Density With Low Bpd Densitysupporting
confidence: 79%
See 1 more Smart Citation
“…As previously reported [6], we have already established very low surface defects in the drift layer with the buffer layer under conventional growth conditions. In this study, we verified the improved growth conditions of the REB layer does not impair the surface quality of the drift layer because it is considered that the surface quality of the buffer layer may affect the quality of the drift layer.…”
Section: Realization Of Low Surface Defect Density With Low Bpd Densitysupporting
confidence: 79%
“…In this paper, through an evaluation of BPDs in the REB layer and the optimization of the growth conditions, we have developed a novel 150 mm 4H-SiC epitaxial wafer product with almost BPD free REB layer for the first time ever. Also, BPDs in the drift layer are almost completely eliminated by maintaining a high BPD to threading edge dislocation (TED) conversion efficiency as previously reported [6].…”
Section: Introductionsupporting
confidence: 61%
“…In the past decades, enormous advancements have been made in the fabrication of commercial substrate and low-defect epitaxial layer growth technology [7][8][9] . The industry standard for SiC epitaxy is growth on 4H-SiC 4 • off-axis Si-face substrates 7,10 at process temperatures of around 1800 K. Defects like stacking faults 11 and triangular defects 12,13 , however, remain a major issue, since these defects limit performance, cause leakage currents, lower the breakdown voltage and increase the onstate resistance [14][15][16] .…”
Section: Introductionmentioning
confidence: 99%