Low-injection minority carrier lifetimes ͑MCLs͒ and deep trap spectra have been investigated in n − 4H-SiC epilayers of varying layer thicknesses, in order to enable the separation of bulk lifetimes from surface recombination effects. From the linear dependence of the inverse bulk MCL on the concentration of Z1/Z2 defects and from the behavior of the deep trap spectra in 4H-SiC p-i-n diodes under forward bias, we conclude that it is Z1/Z2 alone that controls the MCL in this material.

In this work, we report our recently developed 27 kV, 20 A 4H-SiC n-IGBTs. Blocking voltages exceeding 24 kV were achieved by utilizing thick (210 μm and 230 μm), lightly doped N-drift layers with an appropriate edge termination. Prior to the device fabrication, an ambipolar carrier lifetime of greater than 10 μs was measured on both drift regions by the microwave photoconductivity decay (μPCD) technique. The SiC n-IGBTs exhibit an on-state voltage of 11.8 V at a forward current of 20 A and a gate bias of 20 V at 25 °C. The devices have a chip size of 0.81 cm2and an active conducting area of 0.28 cm2. Double-pulse switching measurements carried out at up to 16 kV and 20 A demonstrate the robust operation of the device under hard-switched conditions; coupled thermal analysis indicates that the devices can operate at a forward current of up to 10 A in a hard-switched environment at a frequency of more than 3 kHz and a bus voltage of 14 kV.

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Transmission electron microscopy and KOH etching were used to determine the structure of the carrot defect in 4H-SiC epilayers. The defect consists of two intersecting planar faults on prismatic {11¯00} and basal {0001} planes. Both faults are connected by a stair-rod dislocation with Burgers vector 1∕n [101¯0] with n>3 at the crossover. A Frank-partial dislocation with b=1∕12[44¯03] terminates the basal fault.

Forward voltage instability, or Vf drift, has confounded high voltage SiC device makers for the last several years. The SiC community has recognized that the root cause of Vf drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into Shockley Stacking Faults (SFs) within device regions that experience conductivity modulation. In this presentation, we detail relatively simple procedures that reduce the density of Vf drift inducing BPDs in epilayers to <10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The first low BPD technique employs a selective etch of the substrate prior to epilayer growth to create a near on-axis surface where BPDs intersect the substrate surface. The second low BPD technique employs lithographic and dry etch patterning of the substrate prior to epilayer growth. Both processes impede the propagation of BPDs into epilayers by preferentially converting BPDs into threading edge dislocations (TEDs) during the initial stages of epilayer growth. With these techniques, we routinely achieve Vf stability yields of up to 90% in devices with active areas from 0.006 to 1 cm2, implying that the utility of the processes is not limited by device size.