2006
DOI: 10.4028/www.scientific.net/msf.527-529.141
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Techniques for Minimizing the Basal Plane Dislocation Density in SiC Epilayers to Reduce V<sub>f</sub> Drift in SiC Bipolar Power Devices

Abstract: Forward voltage instability, or Vf drift, has confounded high voltage SiC device makers for the last several years. The SiC community has recognized that the root cause of Vf drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into Shockley Stacking Faults (SFs) within device regions that experience conductivity modulation. In this presentation, we detail relatively simple procedures that reduce the density of Vf drift inducing BPDs in epilayers to <10 cm-2 and permit the fabric… Show more

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Cited by 90 publications
(71 citation statements)
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“…More than 6 cm 2 of the same epilayer has been examined and the entire examined area is confirmed to be Many studies have been carried out to obtain 4H-SiC epilayers with a low density of BPDs, since BPDs in the active region of bipolar devices act as nucleation sites of Shockley faults and cause degradation of on-state conduction performance of devices [13,15]. Successful results have been obtained by Sumakeris et al employing KOHselective etching or lithographic and dry etch patterning of the substrate prior to epitaxial growth in order to enhance the conversion ratio of BPDs into TEDs [46]. They obtained a low BPD density of <10 cm -2 using 8° off substrates and confirmed a minimum drift of on-state voltage of 4H-SiC pin diodes employing the low-BPD-density epilayer.…”
Section: Featurementioning
confidence: 86%
“…More than 6 cm 2 of the same epilayer has been examined and the entire examined area is confirmed to be Many studies have been carried out to obtain 4H-SiC epilayers with a low density of BPDs, since BPDs in the active region of bipolar devices act as nucleation sites of Shockley faults and cause degradation of on-state conduction performance of devices [13,15]. Successful results have been obtained by Sumakeris et al employing KOHselective etching or lithographic and dry etch patterning of the substrate prior to epitaxial growth in order to enhance the conversion ratio of BPDs into TEDs [46]. They obtained a low BPD density of <10 cm -2 using 8° off substrates and confirmed a minimum drift of on-state voltage of 4H-SiC pin diodes employing the low-BPD-density epilayer.…”
Section: Featurementioning
confidence: 86%
“…Since E BPD is very close to E TED , 16 It is also demonstrated that the BPD to TED conversion can be enhanced by growth interruptions, 18,19 substrate KOH etching, [20][21][22] or epilayer post annealing. 23 For SiC bipolar power devices, it is required that the BPD to TED conversion occurs in an n + buffer layer (i.e., BPDs are buried in the n + buffer layer.)…”
mentioning
confidence: 99%
“…Also the conversion of a BPD to TED is energetically favorable as discussed in detail in a reference. 16 The ratio of elastic energy per unit growth length for a BPD (W BPD ) to that for a TED (W TED ) can be derived from the references 16,17 and written aswhere E BPD and E TED are the elastic energies per unit length of dislocation line for a BPD and a TED respectively, and β is the substrate off-axis angle (≤8 It is also demonstrated that the BPD to TED conversion can be enhanced by growth interruptions, 18,19 substrate KOH etching,[20][21][22] or epilayer post annealing. 23 For SiC bipolar power devices, it is required that the BPD to TED conversion occurs in an n + buffer layer (i.e., BPDs are buried in the n + buffer layer.)…”
mentioning
confidence: 99%
“…There have been several reports showing that most of the BPDs convert into threading edge dislocations (TEDs) during epitaxial growth [6][7][8][9] which are less harmful for bipolar devices. Also, different epitaxial techniques have been used to further enhance the conversion of BPD into TED at the epi-substrate interface [10,11] but still the total number of dislocations in the epilayer is the same as in the substrate.…”
Section: Introductionmentioning
confidence: 99%