Extraction procedure for MOS structure fringing gate capacitance components

Modelling and extraction procedure for gate insulator and fringing gate capacitance components of an MIS structure

“…It is worth noticing that the C 1 component is reduced with the increment on t m as (5) indicates. However, because its value is very small with respect to C 2 [14], it has an insignificant impact on the C e dependence with t m . Under this scenario, the reduction of the gate electrode thickness can be considered in order to reduce the impact of the parasitic capacitances on the overall MIS structure behavior.…”

“…The surrounding area, defined as a spacer, is covered by SiO 2 with the aim of including the extrinsic components. Four components can be identified [14]. As was explained previously, those components can be represented by simple capacitive structures, as table 1 shows [15][16][17][18].…”

“…The presence of those parasitic components can produce a significant error on the extracted parameters for short MOS capacitors. Therefore, an extraction methodology able to determine, independently, the area normalized gate capacitance, as well as the fringing extrinsic capacitances for standard MOS structures, has been very recently presented [14]. In this contribution, the methodology is extended for a metalinsulator-semiconductor (MIS) structure considering a high-k dielectric material with the aim of properly determining the EOT as well as the fringing extrinsic components.…”