Modelling and extraction procedure for gate insulator and fringing gate capacitance components of an MIS structure

Tinoco, J. C.; Martinez-Lopez, A. G.; Lezama, G.; Mendoza‐Barrera, C.; Cerdeira, A.; Estrada, M.

doi:10.1088/0268-1242/31/7/075011

Cited by 4 publications

(3 citation statements)

References 19 publications

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“…Good DC figures of merit (FoM) of FinFET and FD planar SOI devices were previously reported in (19,31), respectively. The analog/RF FoM for both advanced devices have been reported in (32)(33)(34)(35)(36)(37)(38)(39)(40)(41)(42)(43)(44). In (34), the variation of transconductance with the voltage gain is chosen as a figure of merit to benchmark various advanced MOSFETs including FinFETs and UTBB.…”

Section: Rf Soi Devicesmentioning

confidence: 99%

(Invited) Current Status and Trends in RF Silicon-on-Insulator Material and Device

Raskin

2018

ECS Trans.

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Radio Frequency (RF) Silicon-on-Insulator (SOI) is today a mainstream technology for several front-end module integrated circuits. The high quality of the trap-rich SOI substrate in terms of low insertion loss and high linearity is at the origin of its commercial success. Partially depleted SOI transistors characterized with a channel length from 180 nm down to 45 nm are currently manufactured on top of the trap-rich substrate. However, there is a growing interest for moving from partially to fully depleted SOI transistors in order to improve the RF and millimeter-waves performance of the transistor at low power consumption. On-going research explores the possibility of combining the best of the digital FD SOI devices and high quality RF SOI substrate to design low power mixed-mode communication system-on-chip.

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Section: Rf Soi Devicesmentioning

confidence: 99%

(Invited) Current Status and Trends in RF Silicon-on-Insulator Material and Device

Raskin

2018

ECS Trans.

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“…As was described in [41][42][43], it is possible to define four basic capacitance structures: (i) parallel-plates, (ii) perpendicularplates or (iii) flat-plates non-parallel capacitor and (iv) fringing field capacitive component, as table 1 shows.…”

Section: Extrinsic Gate Capacitance Modelmentioning

confidence: 99%

Extrinsic gate capacitance compact model for UTBB MOSFETs

Martinez-Lopez

Tinoco

Lezama

et al. 2017

Semicond. Sci. Technol.

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Ultra-thin body and buried oxide transistors have gained attention as candidates for near future CMOS technology nodes. Recent studies have pointed out that the total parasitic gate capacitance becomes an important concern for very-high frequency performance. In this paper a semi-analytical model to describe the total extrinsic gate capacitance for ultrathin silicon body and buried oxide transistors is presented. The developed model considers the main technological parameters and has been verified by finite-element numerical simulations as well as by comparison with experimental measurements. The relative weight of the main parasitic components is addressed as well as their impact over the current gain cut-off frequency. Finally, the possibility to improve the cut-off frequency by about 35% due to the reduction of the parasitic gate capacitance is highlighted.

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“…However, so far, the layout dependence of the fringe capacitance is not considered in the present transistor model and for simplicity, a constant value is generally adopted to perform the circuit simulation [14]. For the gate fringe capacitances, various analytical models have been presented, with the consideration of physical dimension and device structure [15][16][17][18], but LDE is not included. In our previous work [19], a novel test structure is designed to separate C f from C co , and an empirical fitted capacitance increment ΔC f is introduced to characterize the dependence of gate to contact space (CPS) and contact to contact space (CCS).…”

Section: Introductionmentioning

confidence: 99%

Analytical gate fringe capacitance model for nanoscale MOSFET with layout dependent effect and process variations

Sun

Liu

et al. 2018

J. Phys. D: Appl. Phys.

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In this paper, we present an analytical closed model for the gate to source/drain fringing capacitance (Cf) of nanoscale metal oxide semiconductor field effect transistors (MOSFETs), with the consideration of layout dependent effects and process fluctuations. A kind of field-poly structure on shallow trench isolation (STI) is used to separate Cf from other gate-around parasitic capacitances. A significant layout-dependent-effect is found in Cf for the case with high contact density. Based on the device structure, Cf is divided and analytically modeled by three dual-k perpendicular-plate capacitances. The effects of gate to contact space (CPS), contact to contact space (CCS) and the process variations, such as the over-etching of source/drain contact, are taken into account. The proposed model is validated on 40 nm MOSFETs, with a series of layout parameters, and good agreement is obtained between the modeled and measured data over a large range of CPS and CCS. The proposed model can improve the precision for digital and RF circuit simulation in sub-nanometer technology generation.

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Modelling and extraction procedure for gate insulator and fringing gate capacitance components of an MIS structure

Cited by 4 publications

References 19 publications

(Invited) Current Status and Trends in RF Silicon-on-Insulator Material and Device

(Invited) Current Status and Trends in RF Silicon-on-Insulator Material and Device

Extrinsic gate capacitance compact model for UTBB MOSFETs

Analytical gate fringe capacitance model for nanoscale MOSFET with layout dependent effect and process variations

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