Fabricating metal-oxide-semiconductor field-effect transistors on a polyethylene terephthalate substrate by applying low-temperature layer transfer of a single-crystalline silicon layer by meniscus force

Abstract

Articles you may be interested inThreshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor A model of electrical conduction across the grain boundaries in polycrystalline-silicon thin film transistors and metal oxide semiconductor field effect transistors Strain and electrical characterization of metal-oxide-semiconductor field-effect transistor fabricated on mechanically and thermally transferred silicon on insulator films

Fabrication of High Performance Single-Crystalline Silicon Thin Film Transistors on a Polyethylene Terephthalate Substrate

“…This process ensures a good MOS interface, and the SiO 2 layer works as a "blocking" layer that blocks contamination from PET surface. [4] Figure 4 (a) shows I d -V g characteristics of the TFTs fabricated on a transferred c-Si film. The TFT dimensions are L = 3.7 m and W = 3 m.…”

“…In our previous work, a novel low-temperature technique for transferring a c-Si film by meniscus force has been proposed, and the c-Si film which formed in dog-bone shape (with size of 20 × 60 m 2 ) were successfully transferred to a polyethylene terephthalate (PET) substrate at its heatproof temperature or lower. [3,4] In this work, the transfer of smaller dog-bone shape c-Si to the PET sub-strate by the proposed low-temperature layer transfer technique and fabrication of c-Si TFTs are investigated.…”

Meniscus-force-mediated layer transfer technique using single-crystalline silicon films with midair cavity: Application to fabrication of CMOS transistors on plastic substrates

“…To control the threshold voltage, boron ions were injected (at a dosage of 1 × 10 11 cm −2 ) into the channel region. 25) To fabricate p-channel TFTs, on the other hand, the source and drain regions were implanted with boron ions at a dosage of 1.0 × 10 15 cm −2 . The channel region was implanted with phosphorus ions at a dosage of 1.6 × 10 12 cm −2 .…”

“…Moreover, the proposed technique for layer transfer was successfully applied for fabricating n-channel c-Si TFTs on a PET substrate. 25) In the work reported in this paper, we used that technique to fabricate flexible c-Si based CMOS transistors locally at the required positions on plastic substrates and evaluated their performance. Using the patterned SOI layer as a mask, the 300-nmthick buried oxide (BOX) layer was etched by 33% hydrofluoric acid at room temperature to form slim SiO 2 columns that support the SOI layer.…”

Formation of silicon-on-insulator layer with midair cavity for meniscus force-mediated layer transfer and high-performance transistor fabrication on glass

“…Furthermore, we reported the thermal oxidation of silicon-on-insulator (SOI) for the formation of a good MOS interface and the fabrication of high-performance Si TFTs using the transferred films on a substrate of low heat resistance at a low temperature. 19,20) However, the critical issue in MLT to a glass substrate is the low transfer yield of ∼20%. It is necessary to improve this yield.…”