2006
DOI: 10.1063/1.2177549
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Fabrication and characterization of metal-ferroelectric (PbZr0.53Ti0.47O3)-insulator (Dy2O3)-semiconductor capacitors for nonvolatile memory applications

Abstract: Articles you may be interested inElectrical properties of metal-ferroelectric ( Pb Zr 0.53 Ti 0.47 O 3 ) -polysilicon-insulator ( Y 2 O 3 ) -silicon capacitors and field-effect transistorsa) Fabrication and characterization of metal-ferroelectric ( PbZr 0.6 Ti 0.4 O 3 ) -insulator ( La 2 O 3 ) -semiconductor capacitors for nonvolatile memory applications The improvement of retention time of metal-ferroelectric ( Pb Zr 0.53 Ti 0.47 O 3 ) -insulator ( Zr O 2 ) -semiconductor transistors and capacitors by leakage… Show more

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Cited by 68 publications
(42 citation statements)
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“…9 Barrier height for the electrons is ∼0.8 eV, for holes it is ∼1.0 eV at STO/ZnO interface while for electrons at Ag/BTO interface it is ∼ 0.9 eV. 10 Obtained high values of band offset suggest that, Ag/BTO/STO/ZnO MFIS structure is a potential candidate for development of FeFET suitable for non-volatile memory application. Fig.…”
Section: Resultsmentioning
confidence: 90%
“…9 Barrier height for the electrons is ∼0.8 eV, for holes it is ∼1.0 eV at STO/ZnO interface while for electrons at Ag/BTO interface it is ∼ 0.9 eV. 10 Obtained high values of band offset suggest that, Ag/BTO/STO/ZnO MFIS structure is a potential candidate for development of FeFET suitable for non-volatile memory application. Fig.…”
Section: Resultsmentioning
confidence: 90%
“…Compared the C-V curves with the P-E loops in Fig. 3 [28], where d f , d b , ε f , and ε b are the film thicknesses and the relatively dielectric constants of ferroelectric and buffer layers, respectively. We have measured the ε f of the BNdT is about 220 in MFM structure.…”
Section: Resultsmentioning
confidence: 99%
“…The thickness of the interfacial layer (IL) is about 3 nm, which is close to the literature results of 3.7 nm [26] and 3.1 nm [27] for pure HfO 2 deposited on silicon substrate by the method of atomic layer deposition (ALD). In addition, since the dielectric constant of high-k materials is higher than that of conventional SiO 2 , the voltage drop across the ferroelectric layer of ferroelectric/high-k stack structure becomes large according to the coupling ratio of capacitance for two dielectric films in serial [28]. Fig.…”
Section: Methodsmentioning
confidence: 97%
“…The superior characteristics of MFIS include a single-device structure, low power consumption and non-destructive read-out operation [8]. The purpose of the insulator layer is to prevent the reaction and inter-diffusion between the ferroelectric layer and silicon substrate as well as to improve the leakage current and retention property [7]. High-k insulator layer is attractive because proportionally larger voltage can be applied across the ferroelectric layer.…”
Section: Introductionmentioning
confidence: 99%
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