Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channels

Novel gate-all-around polycrystalline silicon nanowire memory device with HfAlO charge-trapping layer

“…This is again attributed to its tiny channel, which contains much fewer grain boundary defects than the 100-nm-thick channel of its planar counterpart. 23) It is well known that the transport of carriers in a poly-Si channel is greatly impeded by the potential barrier at the grain boundaries. 24,25) It was pointed out previously 26) that the modulation of the barrier height at the grain boundaries by the gate bias is more efficient in a multigate NW device than in planar devices.…”

Gas Sensing Ability on Polycrystalline-Silicon Nanowire

“…The n-type poly-Si NW FET consists of two poly-Si NW channels with 75 ± 5 nm in width and 2 μm in length, which was fabricated based on the previously reported procedures. 12,13 The general fabrication steps can be described as followed: (1) a gate dielectric layer is formed on a Si substrate capped with 100 nm SiO 2 layer, followed by chemical vapor deposition (CVD) of nitride oxide. The thickness of nitride oxide was controlled at either 50 or 80 nm to fine tune the electrical properties; (2) the dummy gate is prepared by deposited TEOS z E-mail: pchen@mail.nctu.edu.tw; ysyang@faculty.nctu.edu.tw oxide layer followed by lithography process to define its width and length; (3) the active layer is prepared by deposited a 100 nm-thick amorphous silicon and annealed in N 2 ambient at 600 • C for 24 hrs; (4) the source/drain (S/D) implant was performed by implanted dopants near the top surface of the Si layer but not on the channel area; (5) the Si channels and S/D patterns was revealed and defined its thickness by controlled etching process.…”

“…The grain boundaries, considered as the electron/hole traps, could strongly influence the poly-Si NW's electrical performance. The previous report suggested that poly-Si NW possessed very similar electrical characteristics to the single-Si NW devices [12][13][14][15] especially in the high humidity or in the aqueous environment. 18 The grain boundary defects of poly-Si NW, on the other hand, make it a promising material for gas sensing.…”

Operations of poly-Si nanowire thin-film transistors with a multiple-gated configuration

“…In addition to the SG and TG formed in the fabrication sequence mentioned above, the Si substrate itself serves as the bottom-gate (BG). The process flow and fabricated structure are similar to that described in our previous work [7,12], except that a TG is added lying over the passivation oxide. It should be noted that for the devices characterized in this work, the oxide thickness between the gate and the NW is 100 nm for the BG, 40 nm for the SG, and 200 nm for the TG.…”

“…Note that the unique capability of electrically tuning the threshold voltage in the new NW structure is beneficial not only for circuit applications in electronics, but also for gas and biologic sensing applications. As described in a previous paper [7], the new NW architecture could be applied to chemical and biological sensing purposes, as some portion of the channel is exposed to the environment, as schematically shown in figure 14. After immobilization treatment, receptors are formed on the surface of the exposed channel.…”