Novel gate-all-around polycrystalline silicon nanowire memory device with HfAlO charge-trapping layer

Lee, Ko Hui; Lin, Horng−Chih; Huang, Tiao‐Yuan

doi:10.7567/jjap.53.014001

Cited by 10 publications

(17 citation statements)

References 27 publications

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“…Based on these two features the programming current for fast program operation can be approximated in the range of 10 −2 A=cm 2 , which is consistent with program constraint defined in Table I. 14) Figure 6 shows the P=E characteristics of simulation and experimental data in Ref. 8 being benchmarked to GAA-FG of 6 nm SiO 2 tunnel layer. Generally, it can be observed that the triangular channel of GAA-FG has comparable memory window to 6 nm SiO 2 .…”

Section: Simulation Validation Of Gaa-fgsupporting

confidence: 54%

“…8,9) However, it did not describe the subthreshold degradation of the device. In the absence of short channel effects, interface trap charge is the one who responsible for the subthreshold degradation in GAA structure.…”

Section: Simulation Validation Of Gaa-fgmentioning

confidence: 99%

“…8,9) Although the triangular nanowire provides fast P=E operations, it is not fond to be employed as vertical channel in 3D NAND flash architecture, whereas the punch and plug process favour cylindrical channel instead. [3][4][5][6][7]10) In addition, it also suffers from poor retention due to the charge-trapped around the triangular corners.…”

Section: Introductionmentioning

confidence: 99%

“…The optimized version of asymmetric VARIOTs are then served as the tunnel oxide for GAA-FG where the memory performances are explored, based on its tunneling current P=E characteristics, and 10 years data retention under gate stress, in which are verified and compared with published experimental works on conventional GAA-FG. 8,9) …”

Section: Introductionmentioning

confidence: 99%

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Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Hamzah

Alias

Ismail

2018

Jpn. J. Appl. Phys.

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The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si 3 N 4 , Al 2 O 3 , HfO 2 , and ZrO 2 ) with low-k SiO 2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/ high-k barrier-stacked and extracting their Fowler-Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO 2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO 2 has been obtained using SiO 2 / Al 2 O 3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of %3.6/3.6 V gate stress.

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Section: Simulation Validation Of Gaa-fgsupporting

confidence: 54%

Section: Simulation Validation Of Gaa-fgmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Hamzah

Alias

Ismail

2018

Jpn. J. Appl. Phys.

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“…However, the trade-off between data retention and program/erase speed is the main bottleneck for SONOS devices in replacing floating-gate ones. 12 Recently, high-κ dielectrics have been [13][14][15][16][17][18] Therefore, in this work, to further improve NOR-type flash memory performance, we propose and investigate a type of p-channel charge trapping FOI-MAHAS memory. In the Fabrication process section, we briefly introduce the specific process flow of the p-channel charge trapping FOI-MAHAS memory.…”

mentioning

confidence: 99%

Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure

Hou¹,

Zhang²,

Yin³

et al. 2017

ECS J. Solid State Sci. Technol.

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A type of p-channel fin-on-insulator (FOI) FinFET charge trapping memory devices with HfO 2 charge trapping layer, Al 2 O 3 tunneling layer and blocking layers along with [TiN/W] metal gate (Metal/Al 2 O 3 /HfO 2 /Al 2 O 3 /Si, named as MAHAS in short) have been successfully fabricated. It is found that the new non-volatile memory, named in FOI-MAHAS memory shows better performance as compared with counterparts reported earlier owing to the adoption of p-type FOI channel and specific high-κ dielectrics. The static DC electrical characteristics of the fabricated memory devices including threshold voltage, subthreshold slope, gate breakdown voltage (BV g ), source-drain breakdown voltage (BV DS ) and memory characteristics such as program/erase (P/E) speed, memory window, endurance, and data retention at room temperature with different P/E approaches have been systematically investigated. A larger memory window, lower P/E voltages, improved P/E speed, as well as good data retention and endurance characteristics with band-to-band hot-electron (BBHE) programming are experimentally obtained. The developed p-channel FOI-MAHAS charge trapping memory is promising for the future nano-scaled NOR-type flash memory applications. It is well known that further scaling-down of the conventional bulk planar metal-oxide-semiconductor field-effect transistor (MOSFET) type NOR flash memory becomes very difficult because of the enhanced short-channel effect (SCE) induced by decreased gate control over channel region with the shrinkage of distance between source and drain. It is noteworthy that further scaling of planar NOR-type memory device faces the theoretical limit of source-drain breakdown voltage (BV DS ) which corresponds to the silicon (Si) and silicon dioxide (SiO 2 ) conduction band offset (3.2 eV). Thus, the scaled planar NOR-type flash memories with gate length (L g ) smaller than 100 nm are very difficult to fabricate.1-4 On the other hand, three-dimensional (3D) channel devices, such as fin field-effect transistors (FinFET) or fin-channel tri-gate (TG) device provide excellent SCE immunity thanks to the strong electrostatic controllability of the multiple gates. 5 Moreover, threshold voltage (V th ) variability in the FinFET or TG devices is much smaller than that in the conventional bulk planar MOSFETs because V th variation induced by the random dopant fluctuation (RDF) is negligible in FinFET or TG devices owing to the undoped fin-channels. Additionally, earlier study has shown that the electric field gets significantly enhanced in the curve part of the fin, thus the carrier injection rate from the channel gets substantially increased. As a result, the program and erase speeds of FinFET memory devices get obviously increased with respect to planer counterparts. [6][7][8][9] Recently a novel type of FinFET structure, named as fin-on-insulator (FOI) FinFET has been proposed.10,11 By adopting FOI structure, subsurface leakage paths in FinFETs are eliminated, the drain-induced barrier lowering (DIBL) is further reduced ...

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Charge trapping characteristics of sputter-AlOx/ALD Al2O3/Epitaxial-GaAs-based non-volatile memory

Mahata

Ghosh

Chakraborty

et al. 2021

J Mater Sci: Mater Electron

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Novel gate-all-around polycrystalline silicon nanowire memory device with HfAlO charge-trapping layer

Cited by 10 publications

References 27 publications

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure

Charge trapping characteristics of sputter-AlOx/ALD Al2O3/Epitaxial-GaAs-based non-volatile memory

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