Fabrication and low-temperature transport properties of selectively grown dual-gated single-electron transistors

Motohisa, Junichi; Nakajima, Fumito; Fukui, Takashi; Wiel, W. G. van der; Elzerman, J. M.; Franceschi, S. De; Kouwenhoven, Leo P.

doi:10.1063/1.1470246

Cited by 8 publications

(4 citation statements)

References 16 publications

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“…The size of QD is much smaller than the initial size of the mask opening due to the evolution ofthe facet {1 10} and (1 l)B sidewalls during growth. This SET transistor exhibits variety of physics associated with single electron transport through a QD at low temperature [2,3]. Furthermore, we have fabricated an integrated SET transistor circuit, as shown in Fig.…”

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Formation of nanostructures by selective-area MOVPE and their applications

Motohisa

Fukui

2005

Digest of Papers Microprocesses and Nanotechnology 2005

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Semiconductor nanostructures have been attracting particular attention as fundamental building blocks for nanoscale electronics and photonics in the bottom-up approach. One of the key issues is to realize high-quality and high-density nanostructures with accurate size-and site-controllability. Selective-area (SA) growth on masked substrates using metal organic vapor phase epitaxy (MOVPE) is one of the most effective and versatile techniques to realize nanostructures satisfying these requirements, because the nature of the epitaxial growth is fully utilized and a variety of structures can be realized by appropriate choice of the substrate orientation and design of the mask pattern. Here we present some of our recent results on the formation of nanostructures by SA-MOVPE and their application to nanoscale devices and circuits. Figure 1(a) shows a schematic illustration ofa single electron tunneling (SET) transistor fabricated by SA-MOPVE[l]. Here, a selectively doped GaAs/AlGaAs double heterostructure is grown on a partially SiON-masked GaAs (001) substrate. The crystal growth takes places on the opening region of the mask and a quantum dot (QD) is formed in between two constrictions following the design of the mask pattern.The size of QD is much smaller than the initial size of the mask opening due to the evolution ofthe facet {1 10} and (1 l)B sidewalls during growth. This SET transistor exhibits variety of physics associated with single electron transport through a QD at low temperature [2,3]. Furthermore, we have fabricated an integrated SET transistor circuit, as shown in Fig. 1(b)[4]. The circuit consists of four SET transistors, and operation as AND/NAND logic based on binary decision diagram architecture is demonstrated. More recently, we have achieved XOR operations using multiple-gate SET transistors ( Fig. 1(c)) to realize one-bit adder circuit with three SET transistors in a simplified BDD architecture [5]. When the SA-MOVPE is carried out on (1 1 )B-oriented surface, vertical { 11 0} surfaces appear as facet sidewalls. By using this nature in SA-MOVPE, we have grown free-standing nanowires on masked substrate with circular openings [6]. A typical SEM image of GaAs nanowires are shown in Fig. 2(a). The cross section of the nanowires is hexagonal, reflecting the symmetry of the ( 11 )B plane, and the average lateral size d of the pillars is 0.23um, and their hight is about 1.4 jim. Similar uniform array of hexagonal InGaAs nanowires have also been formed on InP masked substrates. By controlling the directions of the growth with appropriate control of the growth conditions, AlGaAs is overgrown on the sidewalls of GaAs nanowires to form radial or core-shell heterostructures [7], which is promising to realize selectively-doped one-dimensional nanowire transistors as well as to eliminate non-radiative recombination at the nanowire surfaces. Based on these core-shell nanowires, AlGaAs nanotubes (see Fig. 2(b)) have been formed by using anisotropic dry etching and wet chemical preferential etching to confirm t...

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Formation of nanostructures by selective-area MOVPE and their applications

Motohisa

Fukui

2005

Digest of Papers Microprocesses and Nanotechnology 2005

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“…Basic characteristics of the multiple-gate SETs for AND and XOR logic were close to those reported previously. 3,14 Typical Coulomb gaps of the fabricated SETs were from 4.0 to 6.0 mV.…”

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A 1 bit binary-decision-diagram adder circuit using single-electron transistors made by selective-area metalorganic vapor-phase epitaxy

Miyoshi

Nakajima

Motohisa

et al. 2005

Applied Physics Letters

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We demonstrate single-electron operation of a 1 bit adder circuit using GaAs single-electron tunneling transistors ͑SETs͒. GaAs dot and wire coupled structures for the fabrication of SETs were grown by a selective-area metalorganic vapor-phase epitaxy technique. The logic circuit was realized based on a binary decision diagram architecture using Coulomb blockade ͑CB͒ in GaAs dots and switching operations were achieved in a single-electron mode because of the CB effects. Through this architecture, a 1 bit adder circuit was realized with three SETs, two of which were for AND logic and one with two input gates for exclusive OR ͑XOR͒. Both AND and XOR operations were demonstrated at 1.9 K, which indicated successful fabrication of the 1 bit adder. © 2005 American Institute of Physics. ͓DOI: 10.1063/1.1992665͔Single-electron transistors ͑SETs͒ and their integrated circuits are very promising for future large-scale integrated circuits ͑LSIs͒ because of their potential with regard to ultralow power consumption and large-scale integration.1-3 Up to now, SET circuits using complementary metal-oxidesemiconductor ͑CMOS͒-type logic architectures have been developed. [4][5][6][7] However, the practical problems of highdensity integration, such as small gain and the unilateral nature of the devices, impede the replacement of the CMOS logic circuits of current large-scale integrated circuits ͑LSIs͒ in a conventional architecture. Thus, a binary decision diagram ͑BDD͒ -based architecture has been proposed for single-electron logic system applications to overcome these shortcomings. [8][9][10][11] In this architecture, the key device that is a unit element of the circuit is called a BDD node device, and it works as a path switch for single-electron transport between two branches using Coulomb blockade. In this way, the function of any complicated logic can be realized through the combination of node devices. In our previous study, we reported on GaAs AND/NAND logic circuits based on BDD integration of four GaAs single-electron transistors ͑SETs͒ fabricated through selective-area metalorganic vapor-phase epitaxy ͑SA-MOVPE͒.3 This is feasible if a network-like structure of SET arrays is realized, because the BDD logic architecture is based on a graphical representation of the logic. In this letter, we report on the fabrication and experimental operation of a 1 bit BDD adder based on selforganized network-like structures of dot-wire coupled arrays for single-electron circuits. Figures 1͑a͒ and 1͑b͒ show, respectively, a graphic representation and a scanning electron microscope ͑SEM͒ image of the GaAs 1 bit BDD adder. Three SETs are integrated in this circuit, consisting of four ohmic pads ͑T1, T2, T3, T4͒ for the BDD terminals, two main gates ͑MG1, MG2͒, and three control gates ͑CG1, CG2, CG3͒. The main gates correspond to the input for the 1 bit adder. Each control gate is used to form the quantum dot and tunneling barriers and to tune the phase of Coulomb oscillations. 12The operating principle of this circuit as a BDD 1 bit adde...

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“…The circuit consists of four dual-gated SET transistors. 13,14 SE transport in SET transistors is controlled by two main gates ͑MG1, MG2͒ and four control gates ͑CG1, CG2, CG3, CG4͒. Among them, MG1 and MG2, which are the common gates for two transistors, correspond to the logic input for the BDD node X 1 and X 2 , respectively.…”

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“…14 In dual-gated SET transistors, the position of these peaks and valleys can be controlled by adjusting the voltage of control gate CG1 ͑CG2͒. 13,14 In the present condition for CG1 and CG2, the peak and valley of the two COs in the two SET transistors appeared complementarily at V MG1 of approximately Ϫ340 and Ϫ375 mV. Thus, a SE path from T1 ͑ROOT͒ can be set to T2 ͑logic ''1''͒ for V MG1 ϭϪ340 mV, and T4 ͑logic ''0''͒ for V MG1 ϭϪ375 mV.…”

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Single-electron AND/NAND logic circuits based on a self-organized dot network

Nakajima¹,

Miyoshi²,

Motohisa³

et al. 2003

Applied Physics Letters

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We experimentally demonstrated single-electron operations of an AND/NAND logic circuit based on a self-organized GaAs quantum-dot ͑QD͒ network fabricated by applying a selective-area metalorganic vapor-phase epitaxy technique. Single-electron logic operations using four cooperating single-electron tunneling ͑SET͒ transistors has been tested. This logic circuit has an architecture based on a binary decision diagram ͑BDD͒ using a Coulomb blockade ͑CB͒ in GaAs QDs, which is a representation of digital logic functions using directed graphs. BDD node devices consisting of two SET transistors achieved a two-way path switching operation in single-electron mode due to the CB effects which appeared complementarily in the two SET transistors at 1.9 K. We also demonstrated an AND/NAND operation in a logic circuit by integrating two BDD nodes. Single-electron logic circuits have received substantial attention because they have a low power consumption and a high-density integration, which enables adding a new function to present devices. 1,2 This is because single-electron tunneling ͑SET͒ transistors can control the exact number of electrons in a nanoscale island via Coulomb blockade ͑CB͒ effects. To date, SET circuits using complementary-metaloxide-semiconductor ͑CMOS͒-type logic architectures have been developed. [3][4][5][6] However, the practical problems of highdensity integration, such as small gain and the unilateral nature of the devices, impede replacing CMOS logic circuits of current large-scale integrated circuits ͑LSIs͒ in conventional architecture. Thus, an architecture based on binary decision diagram ͑BDD͒ is proposed for SE-logic system applications to overcome these shortcomings. 7,8 In this architecture, the key device as a unit element of the circuit is called a BDD node device, which works as a path switch of SE transport between two branches using CB, 9 and the function of any complicated logic can be realized by the combination of the node devices.Because the BDD logic architecture is based on the graphical representation of the logic, it is feasible if the network-like structure of SET transistors arrays is realized. 10 In this letter, we report on the fabrication and experimental operation of SET logic circuits based on network of GaAs quantum dot ͑QD͒ and quantum wires ͑QWRs͒. Arrays of SET transistors utilizing a QD are fabricated by using selective-area metalorganic vapor-phase epitaxy ͑SA-MOVPE͒ on partially masked GaAs substrates. 3,11,12 Based on these nanostructures, SE BDD logic circuits are constructed by integrating four SET transistors. Figure 1͑a͒ shows an array of SET transistors grown by SA-MOVPE. The unit cell of the array is the region enclosed by the white box and is schematically shown in Fig. 1͑b͒. It consists of four SET transistor structures. As we reported in previous papers, 12,13 each SET transistor structure, consisting of a QD, QWRs, and tunneling barriers, indicated by the white circle in the figure, can be fabricated by SA-MOVPE growth on partially masked GaAs ͑001͒ substra...

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Fabrication and low-temperature transport properties of selectively grown dual-gated single-electron transistors

Cited by 8 publications

References 16 publications

Formation of nanostructures by selective-area MOVPE and their applications

Formation of nanostructures by selective-area MOVPE and their applications

A 1 bit binary-decision-diagram adder circuit using single-electron transistors made by selective-area metalorganic vapor-phase epitaxy

Single-electron AND/NAND logic circuits based on a self-organized dot network

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