Fabrication and MOS interface properties of ALD AlYO3/GeO /Ge gate stacks with plasma post oxidation

Abstract

The realization of Ge gate stacks with thin equivalent oxide thickness (EOT), low interface state density (D it) and small hysteresis is a crucial issue for Ge CMOS. In this study, we propose a new AlYO 3 /GeO x /Ge MOS interface, formed by atomic layer deposition (ALD) AlYO 3 /Ge MOS structures with plasma post oxidation (PPO). Reduction in D it by PPO is found for AlYO 3 /Ge system. A 1.5-nm-thick AlYO 3 /GeO x /Ge interface with 1.25-nm EOT can provide a lower amount of the slow trap density, particularly in the valence band side of Ge, than the control Al 2 O 3 /GeO x /Ge interface and the Y 2 O 3 /GeO x /Ge interface. Deposition of any high-k films on the AlYO 3 /GeO x /Ge structure leads to the increase in the slow trap density to the same level, suggesting the influence of any traps at the interface between the high-k films and AlYO 3 .

Slow Trap Properties and Generation in Al2O3/GeOx/Ge MOS Interfaces Formed by Plasma Oxidation Process

“…Any defects in the insulators in MOS interfaces including Al 2 O 3 − and Ge oxides , could be these slow trap physical origins, which have recently been reported. We have also reported the slow trap behavior of ALD Al 2 O 3 /GeO x /n-Ge MOS interfaces formed by post-PO and n-channel MOSFETs using these MOS interfaces .…”

Effects of Electrical Stress in Solution-Processed Spin-On Glass Dielectric Films: Frequency Dependence

“…Figure 2 shows the frequency dependence of the MOS capacitors comparing the initial characteristics and after 5V electrical stress during different times. It can be observed as a frequency dependence, or also called frequency dispersion, at the initial measurement due to interface states [5,19]. On the other hand, the electrical stress induce charge trapping at the dielectric-semiconductor interface (interface charge).…”

“…On the other hand, the electrical stress induce charge trapping at the dielectric-semiconductor interface (interface charge). This interface charge causes variations in the accumulation capacitance [18][19][20]. It can be observed, that after a long stress time, the characteristics are very similar.…”

III-V/Ge MOS device technologies for low power integrated systems

“…These results suggest that appropriate doping of Y atoms into Ge oxides and Al2O3 near Ge interfaces can reduce the slow trap density and improve the BTI reliability. Thus, we have examined the impact of ALD Y2O3 and AlYO3 gate stacks on the slow trap density [216]. Fig.…”