Fabrication of ultra-thin strained silicon on insulator

Abstract

A bond and etch back technique for the fabrication of 13-nm-thick, strained silicon directly on insulator has been developed. The use of a double etch stop allows the transfer of a thin strained silicon layer with across-wafer thickness uniformity comparable to the as-grown epitaxial layers. Surface roughness of less than 1 nm was achieved. Raman analysis confirms strain remains in the thin silicon layers after the removal of the SiGe that induced the strain. Ultra-thin strained silicon-on-insulator (SSOI) substrates are promising for the fabrication of ultra-thin body and double-gate, strained Si metal-oxide semiconductor field-effect transistors (MOSFETs).

Structural inhomogeneity in silicon-on-insulator probed with coherent X-ray diffraction

“…Systematic studies of SSOI structures by X-ray topography, Raman scattering, atomic force microscopy and cross-sectional high-resolution TEM [18,19] have been carried out, and most of the references indicate that the strain generated by lattice mismatches between SiGe and silicon layer is not affected by further processing such as transferring or annealing of thin silicon films [2,20]. Coherent X-ray diffractive imaging studies on SSOI samples are planned in the near future to obtain a better understanding of the distribution and evolution of strains caused by lattice mismatches between crystals and the causal stresses or pressure.…”

“…SOI based MOSFETs are considered to be one of the best alternatives to conventional bulk-silicon MOSFET technology, however, fabrication of SOI wafers is significantly more technologically challenging as the dimensions of the devices shrink dramatically. State-of-Art lithography-based fabrication techniques [1] are starting to be employed to overcome the possibility of strain arising from SOI fabrication [2].…”

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

“…2, the biaxial tensile strain at an interface, induced by the crystal lattice mismatch between Si and SiGe, can be realized either by growing a thin Si layer on a relaxed SiGe substrate epitaxially 5 or growing strained silicon directly on an insulator by a bond and etch-back technique. 6 Consequently, in the energy band of the strained Si, the sixfolddegenerate valleys are split into two sets of twofold and fourfold bands, giving rise to enhanced carrier transport. Furthermore, the repopulation of the energy bands and the reduction of intervalley phonon scattering boost carrier mobility significantly, especially for bulk nMOSs.…”

“…16 (5) A uniaxially strained device shows much better reliability. 17 (6) Smaller leakages arise from reduced bandgap narrowing, as compared with biaxial tensile stress, which causes much greater band-to-band tunneling (BTBT) leakage. 18 (7) Significantly less strain (59) is required for hole mobility enhancement when applying longitudinal uniaxial compression versus in-plane biaxial tension using the conventional SiGe substrate approach.…”

Wafer bonding in silicon electronics

“…The realization of SSOI wafers from bulk materials is a complex process combining wafer bonding, hydrogeninduced layer transfer, and etch-back methods. Processes using thick SiGe buffer layers were described, for instance, in references [47][48][49], while a process using thin buffer layers was published in Ref. [50].…”