Facet Propagation in Si and SiGe Epitaxy or Etching

Dutartre, D.; Talbot, A.; Loubet, N.

doi:10.1149/1.2355845

Cited by 31 publications

(27 citation statements)

References 9 publications

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“…Anisotropic etch and growth processes are characterized by etch/growth rates along certain crystallographic directions. These rates are known from experiments to primarily depend on the involved materials/etchants and on the process temperature [11]- [13]. Speed functions V that reflect the experimental observations give rise to a non-convex Hamiltonian [15], causing numerical problems at sharp corners.…”

Section: Introductionmentioning

confidence: 99%

The Level-Set Method for Multi-Material Wet Etching and Non-Planar Selective Epitaxy

et al. 2020

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We present numerical methods to enable accurate and robust level-set based simulation of anisotropic wet etching and non-planar epitaxy for semiconductor fabrication. These fabrication techniques are characterized by highly crystal orientation-dependent etch/growth rates, which lead to non-convex Hamiltonians in their description by the level-set equation. As a consequence, instable surface propagation may emerge, leading to unphysical results. We propose a calibration-free Stencil Lax-Friedrichs scheme and an advanced adaptive time-stepping approach, tailored to the level-set speed functions associated with anisotropic etching and epitaxy. The scheme calculates the numerical dissipation based on information about the local geometry and the nature of the etch rates/growth function, which enables an optimized tradeoff between overly rounding of sharp geometric features and stable surface propagation. Furthermore, we introduce the deposition top layer method, which allows for robust handling of multiple material regions in non-planar epitaxy simulations. Both methods are demonstrated in a prototypical implementation, which is used to validate the capability and accuracy of our approaches. In particular, two-dimensional wet etching and three-dimensional epitaxy simulations are performed and characteristic geometry parameters are compared to the ideally expected values, showing robustness and high accuracy.

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Section: Introductionmentioning

confidence: 99%

The Level-Set Method for Multi-Material Wet Etching and Non-Planar Selective Epitaxy

et al. 2020

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“…Guilei Wang 1,2 *, Henry H. Radamson 1,2,3 and Mohammadreza Kolahdouz 4 *Address all correspondence to: wangguilei@ime.ac.cn…”

Section: Author Detailsmentioning

confidence: 99%

“…Selective epitaxy of SiGe material is considered as one of the most important steps in the CMOS processing. This type of growth method was already discovered and highlighted in the 1990s with a focus on optimizing the growth parameters to improve the layer quality of Si/ SiGe multi-layers [1][2][3][4]. The outcome of the initial works showed that {113} and {110} facet planes were mostly dominant, whereas other facet planes, e.g., {119} and {018}, could also appear at certain growth conditions.…”

Section: Introductionmentioning

confidence: 99%

Selective Epitaxy of Group IV Materials for CMOS Application

Wang¹,

Radamson²,

Kolahdouz³

2018

Complementary Metal Oxide Semiconductor

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As the International Technology Roadmap for Semiconductors (ITRS) demands an increase of transistor density in the chip, the size of transistors has been continuously shrunk. In this evolution of transistor structure, different strain engineering methods were introduced to induce strain in the channel region. One of the most effective methods is applying embedded SiGe as stressor material in source and drain (S/D) regions by using selective epitaxy. This chapter presents an overview of implementation, modeling, and pattern dependency of selective epitaxy for S/D application in CMOS. The focus is also on the wafer in and ex situ cleaning prior to epitaxy, integrity of gate, and selectivity mode.

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“…The 3D architecture was designed and manufactured for 22 nm node. SiGe The epi-layers may suffer from several problems e.g., facet formation [44,45], defects, micro/loading, non-uniform strain distribution, surface roughness and pattern dependency effect [46][47][48][49][50]. The pattern dependency happens when the density and size of the transistor vary in a chip.…”

Section: Stress Engineeringmentioning

confidence: 99%

“…This problem can be decreased by optimizing the growth parameters (high HCl partial pressure, low total pressure and high hydrogen carrier gas pressure) and by designing chip layouts where the exposed Si is uniformly distributed over the chip's area to create uniform gas consumption [50]. The epi-layers may suffer from several problems e.g., facet formation [44,45], defects, micro/loading, non-uniform strain distribution, surface roughness and pattern dependency effect [46][47][48][49][50]. The pattern dependency happens when the density and size of the transistor vary in a chip.…”

Section: Stress Engineeringmentioning

confidence: 99%

The Challenges of Advanced CMOS Process from 2D to 3D

Radamson

Zhang

et al. 2017

Applied Sciences

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Abstract:The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

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Facet Propagation in Si and SiGe Epitaxy or Etching

Cited by 31 publications

References 9 publications

The Level-Set Method for Multi-Material Wet Etching and Non-Planar Selective Epitaxy

The Level-Set Method for Multi-Material Wet Etching and Non-Planar Selective Epitaxy

Selective Epitaxy of Group IV Materials for CMOS Application

The Challenges of Advanced CMOS Process from 2D to 3D

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