Fast and accurate processor models for efficient MPSoC design

Abstract

With growing system complexity and ever increasing software content, the development of embedded software for upcoming MPSoC architectures is a tremendous challenge. Traditional ISS-based validation becomes infeasible due to the large complexity.Addressing the need for flexible and fast simulating models, we introduce in this paper our approach of abstract processor modeling in the context of multi-processor architectures. We combine modeling of computation on processors with an abstract RTOS and accurate interrupt handling into a versatile, multi-faceted processor model with several levels of features.Our processor models are utilized in a framework allowing designers to develop a system in a top-down manner using automatic model generation and compilation down to a given MPSoC architecture. During generation, instances of our processor models are integrated into a system model combining software, hardware and bus communication. The generated system model serves for rapid design space exploration and a fast and accurate system validation.Our experimental results show the benefits of our processor modeling using an actual multiprocessor mobile phone baseband platform. Our abstract models of this complex system reach a simulation speed of 300MCycles/sec within a high accuracy of less than 3% error. In addition, our results quantify the speed/accuracy trade-off at varying abstraction levels of our models to guide future processor model designers.

Automated, retargetable back-annotation for host compiled performance and power modeling

“…To further capture dynamic effects, several approaches include dedicated simulation models of micro-architecture features such as caches or branch predictors [25,30] or of complete OS and processor models that include effects of task interleavings or other exceptions [12,24]. Furthermore, there are hybrid models that toggle between host-compiled and ISS-based execution [15,20].…”

Mixed-criticality system modelling with dynamic execution mode switching

“…Many approaches regarding RTOS modelling in discrete event simulators have been proposed throughout the literature [6,18,19]. This paper extends our host-based multitasking RTOS model based on SystemC [12,13] by adding the capability of a global criticality state and the support of dynamic execution modes.…”

Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level

“…On source code level, distinct mechanisms exist to retrieve the timing information for SCI. In [8], [9], the execution times for different types of operations are profiled for test programs. The obtained information is used to estimate the timing for the application software.…”