Fast and Disturb-Free Nonvolatile Flip-Flop Using Complementary Polarizer MTJ

Seo, Yeongkyo; Fong, Xuanyao; Roy, Kaushik

doi:10.1109/tvlsi.2016.2631981

Cited by 15 publications

(6 citation statements)

References 16 publications

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“…2, the power supply to the unused circuit components is temporally turned off during the power-gating mode, thus eliminating wasted standby power consumption. In the nonvolatile logic LSI, the temporal data are stored in a nonvolatile flip-flop (NV-FF) [35][36][37][38][39][40], backed up to the nonvolatile device, and recalled just after power supply is commenced on. The nonvolatile memory does not require backup and recall operations because data is directly stored and loaded to/from the nonvolatile device.…”

Section: Nonvolatile Logicmentioning

confidence: 99%

Design framework for an energy-efficient binary convolutional neural network accelerator based on nonvolatile logic

Suzuki

Oka

Tamakoshi

et al. 2021

NOLTA

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Convolutional neural network (CNN) accelerators, particularly binarized CNN (BCNN) accelerators have proven to be effective for several artificial-intelligence-oriented several applications; however, their energy efficiency should be further improved for edge applications. In this paper, a design framework for an energy-efficient BCNN accelerator based on nonvolatile logic is presented. Designing BCNN accelerators using nonvolatile logic allows for the accelerators to exhibit a massively parallel and ultra-low standby power capability. Thus, a new design can be realized for accelerators that is different from that of conventional accelerators based solely on CMOS. Considering this, we discuss a concrete design considerations of nonvolatile BCNN accelerators. In fact, a systematic design flow of the nonvolatile BCNN is established by combining Vivado HLS and standard electronic design automation tools. As a typical design example, a BCNN accelerator for inferring 32 × 32 pixel MNIST dataset is designed using a 65-nm CMOS technology. By the logic-synthesis result, the proposed BCNN accelerator is estimated to consume 94.2% lower power than that of a conventional BCNN accelerator when the frame rate is 30 frames per second.

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Section: Nonvolatile Logicmentioning

confidence: 99%

Design framework for an energy-efficient binary convolutional neural network accelerator based on nonvolatile logic

Suzuki

Oka

Tamakoshi

et al. 2021

NOLTA

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show abstract

“…Due to the FM nature, MTJ is able to retain its state in the absence of power [13]. Recently, several hybrid MTJ/C-MOS circuits have been proposed such as spin torque sensors [14], spintronic oscillators [15], true random number generator [16], magnetic analog to digital converter [17,18], magnetic full-adders [19][20][21], magnetic compressors [22,23] and magnetic flip-flops [24,25]. The majority of these circuits utilize non-volatile MTJ devices that employ the STT switching technique to match the higher speed of CMOS drivers.…”

Section: Introductionmentioning

confidence: 99%

Differential spin Hall MRAM based low power logic circuits and multipliers

Nehra¹,

Prajapati²,

Kumar³

et al. 2022

Semicond. Sci. Technol.

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A Multiplier is an essential component that dictates the performance of modern computing systems. However, high power dissipation of CMOS multiplier circuits has become a major concern in sub 45 nm technology nodes. Recently, emerging non-volatile memory (NVM) based hybrid circuits have gained a lot of attention due to the prominent feature of negligible static power consumption. Magnetic tunnel junction (MTJ) based spin-torque memories have been used for low power applications. However, spin-transfer torque magnetic random access memory (STT-MRAM) based hybrid CMOS/MTJ circuits exhibit higher write energy and longer incubation delay. In this work, a differential spin Hall (DSH)-MRAM cell is employed for logic and circuit applications. It stores a pair of complementary bits with low write voltage and reduced area. The variability analysis of DSH-MRAM signifies the availability of sufficient margin between different resistance states. Different types of 8x8 and 4x4 hybrid CMOS/MTJ multipliers are analyzed using DSH based adders and logic gates. The proposed multipliers consume approximately 20% less power and exhibit 19% improvement in power-delay product (PDP) characteristics compared to CMOS based multipliers.

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“…This problem is avoided in IoT devices by employing a nonvolatile flip-flop (NVFF) to store the computing data. For this reason, NVFFs have been widely researched by employing various emerging nonvolatile elements, such as field-induced magnetization reversal magnetic tunnel junction (MTJ) [3]- [4], spin-transfer-torque MTJ (STT-MTJ) [5]- [15], complementary polarizer MTJ [16], spin-orbital-torque MTJ [17]- [18], memristor [19]- [22], ferroelectric capacitor (FeCAP) [23]- [26], and ferroelectric field-effect transistor (FeFET) [27]- [28]. Among them, STT-MTJ is suggested to store the computing data as a resistance value (i.e., low and high resistances) before the zero VDD scheme is applied due to its various advantages, such as nonvolatility, high endurance, scalability, and easy integration with CMOS technology [29]- [31].…”

Section: Introductionmentioning

confidence: 99%

Novel MTJ-Based Sensing Inverter Variation Tolerant Nonvolatile Flip-Flop in the Near-Threshold Voltage Region

Choi

2020

IEEE Access

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In recent years, the low power design of Internet of Things devices has become increasingly important. The most basic method to implement a low power design is to reduce static power consumption. In this regard, a spin-transfer-torque magnetic-tunnel-junction-based nonvolatile flip-flop (NVFF) is a promising candidate for storing the computing data while the power is off. However, as the technology node scales down, the process variation increases, leading to a restoration failure in previous NVFFs, especially in the near-threshold voltage (NTV) region. For better energy efficiency when operating the NVFF in the NTV region, this paper presents a novel NVFF that guarantees a target restore yield of 4σ and a target read disturbance margin of 6σ in the NTV region (0.6 V supply voltage), along with auto-zeroing and dynamic reference voltage (DRV) techniques, using only a single capacitor to improve the NVFF's restore yield. The Monte Carlo HSPICE simulation results using industry-compatible 28-nm model parameters show that the proposed NVFF satisfies both the target restore yield and the read disturbance margin, saving 44% restoration time compared with the current state-of-the-art NVFF, which does not satisfy the target restore yield despite having offset cancellation characteristic. INDEX TERMS Auto-zeroing, double sensing margin, dynamic reference voltage (DRV), magnetic tunnel junction (MTJ), near-threshold voltage (NTV), nonvolatile flip-flop (NVFF), sensing inverter variation tolerant (SIVT), sensing margin (SM).

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Fast and Disturb-Free Nonvolatile Flip-Flop Using Complementary Polarizer MTJ

Cited by 15 publications

References 16 publications

Design framework for an energy-efficient binary convolutional neural network accelerator based on nonvolatile logic

Design framework for an energy-efficient binary convolutional neural network accelerator based on nonvolatile logic

Differential spin Hall MRAM based low power logic circuits and multipliers

Novel MTJ-Based Sensing Inverter Variation Tolerant Nonvolatile Flip-Flop in the Near-Threshold Voltage Region

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