Fast Characterization of Threshold Voltage Fluctuation in MOS Devices

Agarwal, Kanak; Hayes, Jerry; Nassif, Sani R.

doi:10.1109/tsm.2008.2004323

Cited by 44 publications

(15 citation statements)

References 21 publications

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“…In this configuration, M 1S and M 2S are part of the DC calibration loop that detects a mismatch between currents I 1 and I 2 , and generates bias voltages V B1 and V B2 individually for each branch. In the absence of mismatches, the gate-source voltage overdrives and drain currents of M 1S and M 2S must be equal [1], which only occurs when Fig. 3.…”

Section: Mismatch Reduction Methodsmentioning

confidence: 99%

“…Since the calibration loop has low-pass filtering nodes, the differential signal integrity is not jeopardized by coupling between M 1 The accuracy of the proposed method relies on the matching between M 1 /M 1S and M 2 /M 2S , which depends on their number of subdevices [5,18]. Let r DVth be the standard deviation of the threshold voltage difference for an unmatched transistor pair.…”

Section: Mismatch Reduction Methodsmentioning

confidence: 99%

“…In addition to higher percent errors with small fabrication dimensions, the threshold voltage mismatch worsens even for neighboring transistors due to the increasing effect of dopant fluctuations in modern CMOS processes [1]. The resulting offsets degrade the performance of analog circuits that rely on device matching.…”

Section: Introductionmentioning

confidence: 99%

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Mismatch reduction technique for transistors with minimum channel length

Onabajo

Silva-Martínez

2011

Analog Integr Circ Sig Process

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An analog calibration technique is presented to improve the parameter matching between transistors in the differential high-frequency signal path of analog CMOS circuits. It can be applied for mismatch reduction in differential broadband amplifiers and direct down-conversion mixers in which short-channel devices are utilized to minimize bandwidth reduction from parasitic capacitances. In general, the proposed methodology is suitable for radio frequency (RF) applications in which direct matching of the transistors is undesired because sophisticated layout practices would increase the coupling between the high-frequency paths. The approach involves auxiliary devices which sense the existing mismatch as part of a feedback loop for error minimization. This technique is demonstrated with a differential amplifier that has a loaded gain and -3 dB frequency of 12.9 dB and 2.14 GHz, respectively. It was designed in 90 nm CMOS technology with a 1.2 V supply. Monte Carlo simulations indicate that the 4.06 mV standard deviation of the amplifier's anticipated input-referred offset voltage improves to 0.76-1.28 mV with the mismatch reduction loop, which is contingent on the layout configuration of the calibration circuitry. The associated drain current mismatch reduction for the transistor pair under calibration in the amplifier core is from 3.1% to 0.6-1.0%.

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Section: Mismatch Reduction Methodsmentioning

confidence: 99%

Section: Mismatch Reduction Methodsmentioning

confidence: 99%

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Mismatch reduction technique for transistors with minimum channel length

Onabajo

Silva-Martínez

2011

Analog Integr Circ Sig Process

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“…Local mismatch is simulated by considering device variations. Voltage threshold of the transistors is modeled as a Gaussian random variable with μ and σ characterized for the process, which is an appropriate assumption for the technology [8].…”

Section: Clock Skew: Probabilistic Approachmentioning

confidence: 99%

Statistical analysis of hold time violations

et al. 2010

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Performance variability is increasing as CMOS devices are continuously scaled down to nanometer dimensions and is posing a major challenge to the profitability of scaled technologies. One of the major goals of a design flow is to satisfy timing constraints without sacrificing area and power. One of the most important tasks of design optimization is to identify and remove setup and hold time violations. Variability issues must be taken into account in order to improve the accuracy of violation removal algorithm.In this manuscript we derive statistical models for flipflop race immunity and clock skew. Then we propose a prob-R. Murgai is currently with Magma Design Automation Inc. abilistic approach for hold-time violations. We present comparisons between probabilistic approach and worst-case approach and prove that the probabilistic method is less pessimistic while being more accurate. We propose a variationaware methodology for computing the delay so as to satisfy the yield constraint.

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“…Integrating circuit monitors with high frequency analog circuits is one strategy that is proposed to increase yield, optimize system performances and reduce the cost of test [1][2][3]: it is well known that device parameters differ from their nominal value due to environmental changes (supply voltage, temperature), manufacturing process variation and intra-die variability, which trend to increase as technology scales down [4]. Moreover, due to the trend toward device shrinking, the complexity, density and operating frequency of both analog and RF integrated circuits (ICs) increase continuously.…”

Section: Introductionmentioning

confidence: 99%