IntroductionWith each semiconductor process node, the impacts on performance of environmental and semiconductor process variations become a larger portion of the cycle time of the product. Simple guard-banding for these effects leads to increased product development times and uncompetitive products. In addition, traditional static timing methodologies are unable to cope with the large number of permutations of process, voltage, and temperature corners created by these independent sources of variation. In this paper we will discuss the sources of variation; by introducing the concepts of systematic inter-die variation, systematic intra -die variation, and intra-die random variation. We will show that by treating these forms of variations differently, we can achieve design closure with less guard-banding than traditional methods.ASIC providers are typically responsible for the performance and yield of the devices they deliver. It is therefore common in the ASIC industry to require timing closure, as measured by a static timing analysis tool, at fast process and slow process timing corners. These corners are supposed to represent the maximum variation that is possible between any two die due to normal manufacturing tolerances. The definition of these fast and slow corners is usually done by moving all of the relevant process parameters (eg. channel length, threshold voltage, etc.) to some statistical limit and developing timing models with these process assumptions. It is also now common for ASIC providers to require timing sign-off assuming some amount of on-chip variation. This additional conservatism is added to account for the intra-die variations which can result in missed timings due to differential process variation (and therefore delays) on the clock and data paths. Environmental condition variations, such as end user voltage and temperature, are also accounted for by running additional static timing corners. In the recent past, these methods were sufficient to guarantee timing, and therefore yield, across the range of the normal manufacturing process window.With continued scaling of CMOS technology however, the numbers of relevant sources of variation and their magnitude have increased. In an attempt to account for this , additional static timing corners are being added to ASIC design flows to account for sources of variation that were previously ignored, such as mismatch between PFET on-current and NFET on-current due to threshold voltage variation.As additional sources of variation become important, either the total guard-band applied during static timing is increased, or the risk of impacting yield is increased. This comes about due to the different delay sensitivities of each path on a design and the inability of the currently available design automation tools to handle the unique sensitivities of each path on the chip without running 2 n timing corners, where n is the number of independent variables of interest. Some paths are predominately sensitive to metal delay while others are predominately sensi...

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Random microscopic fluctuations in the number and location of dopant atoms can cause a large variation in the threshold voltage ( ) of a MOS device. In this paper, we present a technique for fast characterization of random threshold voltage mismatch in MOS devices. Our scatter characterization method measures threshold voltage shift by monitoring the change in gate-to-source voltage for a fixed drain current and drain-to-source voltage . We present circuit schematics to characterize scatter by measuring variation for a large set of devices arranged in an individually addressable array. We report experimental results of scatter measurement from test chips fabricated in 65-nm silicon-on-insulator and 65-nm bulk CMOS processes. We also measure and report the magnitude of local device current mismatch caused by fluctuation.

An optically addressed Reed-Solomon parallel decoder has been designed and fabricated for onedimensional parallel access optical memories. The [15, 9] Reed-Solomon decoder operates on 60 parallel optical inputs and has been demonstrated at a data rate of 300 megabits/s. Compared with equivalent serial decoding solutions, this decoder is shown to be more area efficient and offers reduced latency. An extension to two-dimensional error correction using both the parallel and serial strategies is presented, and comparisons are made in terms of parallelism, page rate, and information rate for the two architectures. A hybrid optoelectronic decoding architecture that uses optical finite-field matrix-vector multipliers is given and is shown to offer error correction at large block sizes and aggregate data rates exceeding 10(12) bits/s.