FastPath: Towards Wire-Speed NVMe SSDs

Stratikopoulos, Athanasios; Kotselidis, Christos; Goodacre, John; Luján, Mikel

doi:10.1109/fpl.2018.00036

Cited by 11 publications

(3 citation statements)

References 13 publications

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“…Based on the FERMAT, [22] added priority services for users. [23] proposed FastPath, which analyzed the impact of the software stack on NVMe performance. The FastPath speeds up operations and reduces overhead by eliminating slow I/O interactions.…”

Section: Introductionmentioning

confidence: 99%

A high performance NVMe host logic engine based on dynamically configurable queues and co-design of NVMe and PCIe

Zhibin,

Yu,

et al. 2024

IEICE Electron. Express

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Aiming at the demand for FPGA-based high-bandwidth NVMe SSD host access, this letter presents an NVMe over PCIe Hardware Acceleration Engine (NoPHAE), which has two innovative aspects. Firstly, an NVMe Queues Engine is integrated into the NoPHAE to enhance I/O performance and reduce resource consumption. The NVMe Queues Engine provides dynamic queue configuration and introduces a virtual completion queue, which reduces resource consumption by 20%. Secondly, a PCIe Acceleration Engine is built in the NoPHAE, which implements the co-design of PCIe and NVMe and optimizes the timing for processing PCIe transport layer transactions, resulting in a significant increase in data throughput. Test results indicate that the sequential read and write speed of the NoPHAE is 7.93 times faster than that of the baseline, and the random read and write performance is two times faster than that of the baseline.

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Section: Introductionmentioning

confidence: 99%

A high performance NVMe host logic engine based on dynamically configurable queues and co-design of NVMe and PCIe

Zhibin,

Yu,

et al. 2024

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…2) Traditional FPGA compute acceleration (for typical single host/single accelerator workloads). 3) Bump-inthe-wire SmartNIC type architectures (for network or storage acceleration [10], [11], [12]). 4) Direct network access for the FPGA fabric control and data plane (allowing disaggregation [13], zero-copy data transfer and avoiding host interaction [14]).…”

Section: Introductionmentioning

confidence: 99%

DiAD – Distributed Acceleration for Datacenter FPGAs

Lant,

Skordalakis,

Paraskevas

et al. 2023

2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)

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The growing demands placed upon modern compute and network resources are far exceeding the capabilities of traditional computer architectures. It is now customary for accelerators to perform the bulk of compute, and this compute is being pushed ever closer to the network. FPGA vendors have brought powerful datacenter cards to the market, combining reprogrammable FPGA fabrics with high bandwidth networking capability. However, the supporting infrastructure has yet to reach maturity, so modern and diverse workloads are not yet able to fully leverage these architectural advances.In this paper we present DiAD; a novel framework providing FPGA firmware and driver support for fully unified, distributed compute and network acceleration across a commodity Ethernet network. We present a far richer feature set and greater flexibility than other existing solutions. We show comparable networking performance from the host when compared to Xilinx's OpenNIC solution. As well as allowing for host networking through the FPGA fabric, we demonstrate reliable data transfer directly between FPGA fabrics without host intervention, and show native memory transactions sent over the network supporting pointer-chasing workloads. We achieve line rate for dataflow type communication and approach line rate for larger native memory transfers (87G). This is the author's version of the work. It is made available only for personal use. Not for redistribution. The definitive Version of Record is to be published in the proceedings of the 33rd International Conference on Field-Programmable Logic and Applciations (FPL'23), Sept 4-8, 2023.1 DiAD focuses on AMD/Xilinx devices as the use of the proprietary QDMA IP is central to the design.

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“…It is used to investigate whether the researched object is working normally and whether there are hidden safety hazards, so as to evaluate the original calculation, design and construction. The vibration detection of the structure used mechanical instruments [1]. in the early stage, and the frequency was measured with a spring based on the principle of resonance.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of an optical fiber sensing based vibration monitoring system

Sun¹,

Liu²,

Eldean³

2021

J. vibroeng.

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Vibration analysis is generally used in the industries for condition monitoring of various electromechanical equipment. For the predictive maintenance of the industry equipment, several techniques have been applied which are based on capacitive and piezoelectric accelerometers. However, they possess several real time problems due to the negative influence of electromagnetic interference. The major problem lies in the detection and transmission of various physical parameters in the noisy and harsh environment. In order to solve the weak points of commonly used structural vibration detection sensors that are easily affected by the harsh environment of the engineering site, the principle of optical fiber sensing is studied, and the system optical path is designed based on MZ interference technology. In this work, a special data acquisition and processing software is developed to acquire the sensed data and the vibration detection is carried out on the steel cantilever structure pasted with fiber optic sensors. Extraction using FFT and pattern recognition through bp neural network yields the system accuracy rate of 96.7 %. The proposed interference type optical fiber technology provides a novel approach for real-time monitoring of engineering structure vibration laying the foundation for the research of intelligent buildings.

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FastPath: Towards Wire-Speed NVMe SSDs

Cited by 11 publications

References 13 publications

A high performance NVMe host logic engine based on dynamically configurable queues and co-design of NVMe and PCIe

A high performance NVMe host logic engine based on dynamically configurable queues and co-design of NVMe and PCIe

DiAD – Distributed Acceleration for Datacenter FPGAs

Design and implementation of an optical fiber sensing based vibration monitoring system

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