Fault-diagnosis-based technique for establishing RTL and gate-level correspondences

Abstract

In this paper, we address an important problem associated with hierarchical design flows (termed the mapping problem): identifying correspondences between a signal in a high-level specification and a net in its lower level implementation. Conventional techniques use shared names to associate a signal with a net whenever possible. However, given that a synthesis flow may not preserve names, such a solution is not universally applicable. This work provides a robust framework for establishing register-transfer level (RTL) signal to gate-level net correspondences for a given design. Our technique exploits the observation that circuit diagnosis provides a convenient means for locating faults in a gate-level network. Since our problem requires locating gate-level nets corresponding to RTL signals, we formulate the mapping problem as a query whose solution is provided by a circuit diagnosis engine. Our experimental work with industrial designs for many mapping cases shows that our solution to the mapping problem is 1) fast and 2) precise in identifying the gate-level equivalents (the number of nets returned by our mapping engine for a query is typically one or two even for designs with tens of thousands of VHDL lines).

Logic-level analysis of high-level faults

“…The strategy proposed in [10] works in a similar way. The authors introduce a stuck-at fault at the signal of interest in the RTL description.…”

“…Formal equivalence checkers are used to this purpose, however they require a lot of resources in terms of time and memory. In [10] an interesting fault simulation-based approach is proposed. The authors exploit the fact that circuit diagnosis provides an effective method for identifying a fault location in the circuit.…”

A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification

“…[9] proposed a method of finding candidates for functionally equivalent nets of a given bit-sliced RTL signal line using fault diagnosis techniques. In this paper, their method is utilized to solve the signal line mapping problem.…”

“…A set of the nets having equivalent faults is referred to as E Gv . Steps 1 to 3 are the same as the procedure for finding a functionally equivalent signal line by using the fault diagnosis technique in [9]. In [9], the complete test set T for the detectable faults in a gate level circuit is used as the input patterns for fault diagnosis.…”

“…Signal line mapping is achieved by checking the equivalence between signal lines and all the gate level nets; however, it is obviously not practical. Therefore, we use the method that finds candidates of the functionally equivalent nets from a gate level circuit by using a diagnosis technique [9].…”