Fault Modeling for the Testing of Mixed Integrated Circuits

Abstract

The goal of the research described in this paper is to introduce a fault-modeling technique for simulating defective analog components in Mixed Analog/Digital Integrated Circuits. The proposed faultmodeling strategy has been implemented to develop analog fault models representing the effect of spot defects in CMOS circuits. Results from an initial study of opamps are summarized and detailed results from onc example are included as an illustration of the faultmodeling process.

A Comprehensive Approach for Modeling and Diagnosis of Various Faults in Analog VLSI Circuits

“…For fault detection, use R=1000GΩ for open circuit resistance and R=.01Ohm for short circuit resistance. And capacitor values are C=0.0001pF for short circuit capacitance and C=100µF for open circuit capacitance [17][18][19]. The frequency used for calculation of catastrophic fault in multiple input multiple output circuit is 1 kHz.…”

Defect-based test optimization for analog/RF circuits for near-zero DPPM applications

“…Defect oriented test methodologies [4], [5] have been proposed to address the requirement of low-cost defect screening. Defect-based test generation and optimization enables even small test lists to identify a large portion of the defects.…”

Metrics, techniques and recent developments in mixed-signal testing

“…An area of research that is gaining some ground in mixed-signal testing is the concept of fault modeling [13] [14]. Fault modeling is a concept that has its roots in digital testing [15].…”