Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment

Barbirotta, Marcello; Mastrandrea, Antonio; Menichelli, Francesco; Vigli, Francesco; Blasi, Luigi; Cheikh, Abdallah; Sordillo, Stefano; Gennaro, Fabio Di; Olivieri, Mauro

doi:10.1109/dft50435.2020.9250871

Cited by 21 publications

(14 citation statements)

References 13 publications

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“…The FI approach adopted to evaluate the proposed microarchitecture scheme is similar to that reported in [50].…”

Section: B Time-frame-span Methodologymentioning

confidence: 99%

“…On the other hand, the design reported in [40] exhibits the highest overhead in terms of both time and hardware resources. The works in [43], [44], and [36] present the error percentage for each benchmark and use a random FI on the entire architecture, allowing us to perform a comparison, although the confidence level of the results is limited by the differences in the number of randomly injected faults and the statistical error margin [50]. As introduced in [43], to compare two different FT design approaches; it is possible to refer to the normalized failure percentage (NFP), obtained by dividing the failure percentage of the protected microarchitecture by the failure percentage obtained on the unprotected version of the same microarchitecture subjected to the same FI for all the designs to be compared.…”

Section: Comparison With Existing Fault-tolerant Risc-v Design Case S...mentioning

confidence: 99%

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Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

et al. 2022

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Fault management in digital chips is a crucial aspect of functional safety. Significant work has been done on gate and microarchitecture level triple modular redundancy, and on functional redundancy in multi-core and simultaneous-multi-threading processors, whereas little has been done to quantify the fault tolerance potential of interleaved-multi-threading. In this study, we apply the temporal-spatial triple modular redundancy concept to interleaved-multi-threading processors through a design solution that we call Buffered triple modular redundancy, using the soft-core Klessydra-T03 as the basis for our experiments. We then illustrate the quantitative findings of a large fault-injection simulation campaign on the fault-tolerant core and discuss the vulnerability comparison with previous representative fault-tolerant designs. The results show that the obtained resilience is comparable to a full triple modular redundancy at the cost of execution cycle count overhead instead of hardware overhead, yet with higher achievable clock frequency.INDEX TERMS Circuit faults, digital integrated circuits, fault detection, fault tolerant computing, field programmable gate arrays, microprocessors, multithreading, radiation hardening (electronics), redundancy, robustness.Open Access funding provided by 'Università degli Studi di Roma ''La Sapienza''' within the CRUI CARE Agreement

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“…The FI approach adopted to evaluate the proposed microarchitecture scheme is similar to that reported in [50].…”

Section: B Time-frame-span Methodologymentioning

confidence: 99%

Section: Comparison With Existing Fault-tolerant Risc-v Design Case S...mentioning

confidence: 99%

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

et al. 2022

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“…To validate the resilience of both architectures, we implemented a Time Frame Spanning fault-injection (FI) simulation [24], within a Universal Verification Methodology (UVM) environment able to simulate SEU faults hitting synchronous registers in the design. We, furthermore, implemented a classical random Monte Carlo FI simulation specifically devoted to analyzing the potential improvement given by an ideal memory-scrubbing unit in the SPMs of the VCUs.…”

Section: Validationmentioning

confidence: 99%

“…The Time Frame Spanning methodology [24] divides the whole execution time into M different intervals called time frames. Unlike classical Monte Carlo FI methods, the approach performs the deterministic injection of many faults within the architecture in a specific time frame within the total execution time for each target bit in the hardware architecture.…”

Section: Failure Probability Estimation With Time Frame Spanning Fimentioning

confidence: 99%

Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes

Barbirotta,

Cheikh,

Mastrandrea

et al. 2023

Electronics

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High-performance embedded systems with powerful processors, specialized hardware accelerators, and advanced software techniques are all key technologies driving the growth of the IoT. By combining hardware and software techniques, it is possible to increase the overall reliability and safety of these systems by designing embedded architectures that can continue to function correctly in the event of a failure or malfunction. In this work, we fully investigate the integration of a configurable hardware vector acceleration unit in the fault-tolerant RISC-V Klessydra-fT03 soft core, introducing two different redundant vector co-processors coupled with the Interleaved-Multi-Threading paradigm on which the microprocessor is based. We then illustrate the pros and cons of both approaches, comparing their impacts on performance and hardware utilization with their vulnerability, presenting a quantitative large-fault-injection simulation analysis on typical vector computing benchmarks, and comparing and classifying the obtained results. The results demonstrate, under specific conditions, that it is possible to add a hardware co-processor to a fault-tolerant microprocessor, improving performance without degrading safety and reliability.

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“…It explores several fault tolerance techniques such as spatial and temporal redundancy, ECCs, and watchdog monitoring. A detailed fault resilience analysis for a TMR variant of Klessydra is performed in [9]. SHAKTI-F [10] achieves SEE tolerance for a 5-stage inorder microprocessor while keeping area and performance penalties low.…”

Section: Related Workmentioning

confidence: 99%

A Framework for Fault Tolerance in RISC-V

Dorflinger

Kleinbeck

Albers

et al. 2022

2022 IEEE Intl Conf on Dependable, Autonomic and Secure Computing, Intl Conf on Pervasive Intelligence and Computing, Intl Conf

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Microcontrollers require protection against transient and permanent faults when being utilized for safetycritical and highly reliable applications. Fail safe Dual Core Lockstep architectures are widely used in the automotive domain; the aerospace domain utilizes fail functional TMR or higher redundancy. This work incorporates fault tolerance techniques of those domains into a framework for RISC-V processors. The implemented fault tolerance components are highly configurable to satisfy various dependability requirements. The cost of applied fault tolerance mechanisms is evaluated for both an FPGA and an ASIC implementation. Fault injection tests prove the effectiveness for error detection and cover both transient and permanent faults in logic and memories. New methods are introduced to minimize the error detection latency and achieve a reduction of up to 79%.

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Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment

Cited by 21 publications

References 13 publications

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes

A Framework for Fault Tolerance in RISC-V

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