Fault-resilient decoders and memories made of unreliable components

Vasić, Bane; Ivaniš, Predrag; Brkic, Srdan; Ravanmehr, Vida

doi:10.1109/ita.2015.7308978

Cited by 12 publications

(8 citation statements)

References 28 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A similar SF result shows that the errors introduced in estimating Markov random field models can be partially canceled and benefit end-to-end inference performance [36]. SF effects due to noise in computational elements, rather than graphical model structure errors as here, have been observed in [27], [29], [37] and later specifically in LDPC decoders [23], [25].…”

Section: B Performance Analysissupporting

confidence: 62%

See 1 more Smart Citation

Performance of LDPC Decoders With Missing Connections

Chang

Chatterjee

Varshney

2017

IEEE Trans. Commun.

View full text Add to dashboard Cite

Due to process variation in nanoscale manufacturing, there may be permanently missing connections in information processing hardware. Due to timing errors in circuits, there may be missed messages in intra-chip communications, equivalent to transiently missing connections. In this work, we investigate the performance of message-passing LDPC decoders in the presence of missing connections. We prove concentration and convergence theorems that validate the use of density evolution performance analysis. Arbitrarily small error probability is not possible with missing connections, but we find suitably defined decoding thresholds for communication systems with binary erasure channels under peeling decoding, as well as binary symmetric channels under Gallager A and B decoding. We see that decoding is robust to missing wires, as decoding thresholds degrade smoothly. Moreover, there is a stochastic facilitation (SF) effect in Gallager B decoders with missing connections. We also conduct finite-length simulations, compare the decoding sensitivity to channel noise and to missing wiring, and perform preliminary error-tolerant manufacturing yield analysis.

show abstract

Section: B Performance Analysissupporting

confidence: 62%

“…SF in decoding was observed with transient errors in computation, rather than with missing connections, initially in memory recall[27],[29] and then in communications[23],[30].…”

mentioning

confidence: 99%

Performance of LDPC Decoders With Missing Connections

Chang

Chatterjee

Varshney

2017

IEEE Trans. Commun.

View full text Add to dashboard Cite

show abstract

“…In addition, a simple probabilistic gradient decent bit-flipping decoder, recently proposed by Al Rasheed et al [21], achieves high level of fault-tolerance. Recently, Vasić et al [22] showed that probabilistic behavior of the Gallager-B decoder due to unreliable components can lead to the improved performance. This resulted in an increased interest in hard-decision decoders.…”

Section: Introductionmentioning

confidence: 99%

Majority Logic Decoding Under Data-Dependent Logic Gate Failures

Brkic

Ivaniš

Vasić

2017

IEEE Trans. Inform. Theory

Self Cite

View full text Add to dashboard Cite

A majority logic decoder made of unreliable logic gates, whose failures are transient and datadependent, is analyzed. Based on a combinatorial representation of fault configurations a closed-form expression for the average bit error rate for an one-step majority logic decoder is derived, for a regular low-density parity-check (LDPC) code ensemble and the proposed failure model. The presented analysis framework is then used to establish bounds on the one-step majority logic decoder performance under the simplified probabilistic gate-output switching model. Based on the expander property of Tanner graphs of LDPC codes, it is proven that a version of the faulty parallel bit-flipping decoder can correct a fixed fraction of channel errors in the presence of data-dependent gate failures. The results are illustrated with numerical examples of finite geometry codes.

show abstract

“…This surprising effect we first observed in the case of von Neumann failures [20], [39] and showed that message perturbations caused by gate failures can help decoder to escape from trapping sets. Furthermore, in the infinite number of iterations all trapping sets break, and the decoding process always converge to a valid codeword.…”

Section: Definitionmentioning

confidence: 73%

Hard-decision decoding of LDPC codes under timing errors: Overview and new results

Brkic

Ivaniš

Vasić

2017

2017 25th Telecommunication Forum (TELFOR)

Self Cite

View full text Add to dashboard Cite

Abstract-This paper contains a survey on iterative decoders of low-density parity-check (LDPC) codes built form unreliable logic gates. We assume that hardware unreliability comes from supply voltage reduction, which cause probabilistic gate failures, called timing errors.We are able to demonstrate robustness of simple Gallager B decoder to timing errors, when applied on codes free of small trapping sets, as well as positive effects that timing errors have on the decoding of codes with contains small trapping sets. Furthermore, we show that concept of guaranteed error correction can be applied to the decoders made partially from unreliable components. In contrast to the decoding under uncorrelated gate failures, we prove that bit-flipping decoding under timing errors can achieve arbitrary low error probability. Consequently, we formulate condition sufficient that memory architecture, which employs bit-flipping decoder, preserved all stored information.

show abstract

Fault-resilient decoders and memories made of unreliable components

Cited by 12 publications

References 28 publications

Performance of LDPC Decoders With Missing Connections

Performance of LDPC Decoders With Missing Connections

Majority Logic Decoding Under Data-Dependent Logic Gate Failures

Hard-decision decoding of LDPC codes under timing errors: Overview and new results

Contact Info

Product

Resources

About