Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities

Das, Shantanu; Ramamoorthy, C. V.; Assaf, Mansour H.; Petriu, Emil M.; Jone, Wen-Ben

doi:10.1109/19.982974

Cited by 40 publications

(26 citation statements)

References 25 publications

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“…As the cost of testing is becoming the single major component of the manufacturing expenses of a new product, BIST tends to reduce production and maintenance costs through improved diagnosis. Several companies such as Motorola, AT&T, IBM and Intel have incorporated BIST in many of their products [1], [3]--- [8].…”

Section: Introductionmentioning

confidence: 99%

Designing elementary-tree space compressors using AND/NAND and XOR/XNOR combinations

Malan

Das

Biswas

et al. 2015

2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings

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Implementing aliasing-free (zero-aliasing) space compressors for built-in self-testing of very large scale integration circuits and systems is of great significance, especially in view of the technological paradigm shift in recent years from system-on-board to system-on-chip design. This paper investigates and provides new approach to realizing aliasing-free elementary-tree space compaction hardware targeting specifically embedded cores-based system-on-chips for single stuck-line faults, extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response data outputs of the circuit under test, the paper introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to twoinput AND/NAND and XOR/XNOR logic. The process is illustrated in the paper with details of synthesis of space compressors for the International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 full-scan sequential benchmark circuits using fault simulation programs ATALANTA, FSIM and HOPE, exemplifying the relevance of the technique from the standpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, making it thus a logical choice in commercial design environments. Keywords-Built-in self-testing in very large scale integration, cores-based system-on-chips, fault detection compatibility and conditional fault detection compatibility, space compression.This full text paper was peer-reviewed at the direction of IEEE Instrumentation and Measurement Society prior to the acceptance and publication.978-1-4799-6144-6/15/$31.00 ©2015 IEEE

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Section: Introductionmentioning

confidence: 99%

Designing elementary-tree space compressors using AND/NAND and XOR/XNOR combinations

Malan

Das

Biswas

et al. 2015

2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings

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“…W ITH increasing complexity in systems design from increased levels of integration densities in digital design, better and more effective methods of testing are required to ensure reliable operations of IC chips-the mainstay of today's many sophisticated systems. The concept of testing has a broad applicability, and finding highly efficient testing techniques that ensure correct system performance has assumed significant importance [1]- [28]. In general, the cost of testing integrated circuits (ICs) is rather prohibitive; it ranges from 35% to 55% of their total manufacturing cost.…”

Section: Introductionmentioning

confidence: 99%

“…The conventional testing techniques of digital circuits require application of test patterns generated by a test pattern generator (TPG) to the circuit under test (CUT) and comparing the responses with known correct responses. However, for large circuits, because of higher storage requirements for the fault-free responses, the test procedures become rather expensive and hence alternative approaches are sought to minimize the amount of needed storage [26]- [28].…”

Section: Introductionmentioning

confidence: 99%

“…It combines the concepts of both built-in test (BIT) and self-test (ST) in one termed built-in self-test (BIST). In BIST, test generation, test application, and response verification are all accomplished through built-in hardware [1], [2], [4], [17], [26]- [28], which allows different parts of a chip to be tested in parallel, reducing the required testing time, besides eliminating the need for external test equipment. As the cost of testing is becoming the major component of the manufacturing cost of a new product, BIST thus tends to reduce manufacturing and maintenance costs through improved diagnosis.…”

Section: Introductionmentioning

confidence: 99%

“…The subject paper aims on the response compaction process of built-in self-testing techniques that translates into a process of reducing the test response from the CUT to a signature. Instead of comparing bit-by-bit the fault-free responses to the observed outputs of the CUT as in conventional testing methods, the observed signature is compared to the correct one, thereby reducing the storage needed for the correct circuit responses [17], [26]- [28]. The response compaction in BIST is carried out through a space compaction unit followed by time compaction.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering

Das

Liang

Petriu

et al. 2002

IEEE Trans. Instrum. Meas.

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The synthesis of space-efficient support hardware for built-in self-testing (BIST) is of critical importance in the design and manufacture of today's sophisticated VLSI circuits, and a number of efficient algorithms have been proposed in the literature for this purpose. The subject paper reports new techniques that facilitate designing such space-efficient BIST support circuits using knowledge of compact test sets, with the target objective of minimizing the storage requirements for the circuit under test (CUT), while retaining the fault coverage information as best as possible. The suggested techniques take advantage of some well-known concepts of conventional switching theory, particularly those of cover table and frequency ordering, as commonly utilized in the minimization of switching functions, in conjunction with a new measure of failure probability in case of stochastic dependence of line errors, besides knowledge of Hamming distance, sequence weights, and derived sequences as previously used by the authors in sequence characterization, in the selection of specific logic gates for merger of an arbitrary number of output bit streams from the CUT. The outputs coming out of the space compactor may eventually be fed into a time compactor to derive the CUT signatures. The developed techniques guarantee good design with high fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable area overhead. Design algorithms are provided in the paper, and the simplicity and ease of their implementations are demonstrated with various examples. In particular, the paper gives results on extensive simulation runs on the ISCAS 85 combinational benchmark circuits with ATALANTA, FSIM, and COMPACTEST programs which confirm the merit of the approaches under conditions of both stochastic independence and dependence of multiple line output errors. A performance comparison of the designed space compactors with conventional linear parity tree space compactors as benchmark is also provided, which demonstrates the enhanced tradeoff for the new circuits in terms of fault coverage and the CUT resources consumed in comparison with the existing design methodologies.

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Design of Aliasing Free Space Compressor in BIST with Maximal Compaction Ratio Using Concepts of Strong and Weak Compatibilities of Response Data Outputs and Generalized Sequence Mergeability

Das

Assaf

Petriu

et al. 2002

Lecture Notes in Computer Science

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Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities

Cited by 40 publications

References 25 publications

Designing elementary-tree space compressors using AND/NAND and XOR/XNOR combinations

Designing elementary-tree space compressors using AND/NAND and XOR/XNOR combinations

Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering

Design of Aliasing Free Space Compressor in BIST with Maximal Compaction Ratio Using Concepts of Strong and Weak Compatibilities of Response Data Outputs and Generalized Sequence Mergeability

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