Proceedings of the 9th International Symposium on Networks-on-Chip 2015
DOI: 10.1145/2786572.2788709
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Fault-Tolerant 3D-NoC Architecture and Design

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Cited by 4 publications
(1 citation statement)
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“…3D network-on-chip (NoC) [34,35] has been demonstrated as a promising infrastructure to integrate increasing transistors in multiple tiers. 3D NoC eliminates the need for long global interconnects and reduces the voltage droop and power consumption on long wires.…”
Section: Example Analysismentioning
confidence: 99%
“…3D network-on-chip (NoC) [34,35] has been demonstrated as a promising infrastructure to integrate increasing transistors in multiple tiers. 3D NoC eliminates the need for long global interconnects and reduces the voltage droop and power consumption on long wires.…”
Section: Example Analysismentioning
confidence: 99%