Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip

Bhanu, P. Veda; Soumya, J

doi:10.1016/j.sysarc.2021.102026

Cited by 14 publications

(5 citation statements)

References 37 publications

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“…Compared to the approaches [9], [10], the throughput obtained for a specific link fault in the FTTG using our approach is high, but it is low when compared with [5]. According to [41], the throughput is defined as the ratio of total number of data packets received with in the time window to the maximum receive time. Therefore, the throughput of a network depends on the number of intermediate routers participated in the routing path for each edge in the application.…”

Section: ) Dynamic Simulation Resultsmentioning

confidence: 99%

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA

et al. 2021

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Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, faulttolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant applicationspecific topology-based NoC design and its prototype on an FPGA. To place spare links in the ASNoC topology, a meta-heuristic algorithm based on Particle Swarm Optimization (PSO) is proposed. By taking link faults into account in ASNoC design, we also propose an application mapping heuristic and a tablebased fault-tolerant routing algorithm. Experiments are carried out for a specific link and any link fault in fault-tolerant topologies generated by our approach and approaches reported in the literature. For the experimentation, we used the multi-media applications Picture-in-Picture (PiP), Moving Pictures Expert Group (MPEG) -4, MP3Encoder, and Video Object Plane Decoder (VOPD). Experiments are run on software and hardware platforms. The static performance metric communication cost and the dynamic performance metrics network latency, throughput, and router power consumption are examined using software platform. In the hardware platform, the Field Programmable Gate Array (FPGA) is used to validate proposed fault-tolerant topologies and analyze performance metrics such as application runtime, resource utilization, and power consumption. The results are compared with the existing approaches, specifically Ring topology and its modified versions on both software and hardware platforms. The experimental results obtained from software and hardware platforms for a specific link and any link fault show significant improvements in performance metrics using our approach when compared with the related works in the literature.

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Section: ) Dynamic Simulation Resultsmentioning

confidence: 99%

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA

et al. 2021

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“…SoW [49] =System on Wafer,ÏLXÚó §ØƒÀ ,ò¬ ù˜²L5!¤Ù5Úp-5 ó² ² ÿÐ XÚ8¤ ¡, ¡º˜¬ 8¤ p'°!pU Ú$ò´U,`³,é ˜^"$› Ñ" XÚ8¤ó §Eâ´‚,lJ¦ ‡ ó²Eâ?Ú,?•J¦XÚ?õU!5U † U 8I¢ y. Ÿ´ ² ë 'X -|" [51] ,E,5XÚ é&´"ë 'X3 XÚ¥Pk•- ‡/ ".3SDSoW¥,˜ ‡p-Ý!rOE ‡ ¬þpë äé¬þXÚ õU!5U Ú UÓ -'- ‡,¬þpë äØ= ‡¢y ‡ykë ä p-Ý!OE5 , …" ‡¢yp (¹ÚrOE ‡.^ ‡½Âpë [48] IO [52,53] !^ ‡½Âpë ä [54] !´d †Pl››Å› [55] !N †5 O [56] !OEÿ5 O [57] †›E ˜X '…Eâ. [58,59] ,Ù«a!…”

Section: Lsoc Sdsowunclassified

从SoC到SDSoW：微电子发展的新范式

Wu,

Liu,

Shen

et al. 2024

Sci. Sin.-Inf.

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“…Fault-tolerant approaches such as [32][33][34][35][36][37][38][39][40] are trying to deal with various faults that may happen in the NoC environment and make unreliable NoCs safe environments that can execute the tasks successfully.…”

Section: Fault Tolerance-aware Schemesmentioning

confidence: 99%

Towards Task Mapping Approaches in Network on Chips: A Comprehensive Survey

Màsdàrí

2023

Preprint

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One of the main stages of Network on Chip (NoC) is task mapping where the application tasks are mapped to the processing resources. Task mapping decisions have a direct impact on the NoC performance and can be classified as static or dynamic mapping methods. In this paper, we carry out a comprehensive systematic study of task mapping schemes in various NoCs. For this purpose, firstly, an overview of the task mapping's main concepts is presented. Then, a taxonomy of the mapping schemes regarding their objectives and applied mapping factors is presented and the studied schemes are categorized into fault-tolerant schemes, congestion-aware schemes, communication-aware approaches, temperature-aware methods, and energy-aware schemes. Afterward, their main contributions, provided services, and drawbacks of the proposed studies in the literature are illustrated. Moreover, a comprehensive discussion of various features of the investigated mapping methods is presented and issues such as the applied algorithms, simulators, datasets, and evaluation metrics are discussed. Finally, the concluding issues and open research areas are highlighted.

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Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip

Cited by 14 publications

References 37 publications

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA

从SoC到SDSoW：微电子发展的新范式

Towards Task Mapping Approaches in Network on Chips: A Comprehensive Survey

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