Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology

Bossen, D. C.; Kitamorn, A.; Reick, Kevin; Floyd, Michael S.

doi:10.1147/rd.461.0077

Cited by 38 publications

(15 citation statements)

References 5 publications

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“…Redundancy for fault-tolerance can be incorporated in different levels of granularity. Commercial high-availability multiprocessor systems like the IBM p690 have been designed to exploit redundancy at chip and module level [25]. These systems can map detected failures to individual CPUs and achieve system recovery by de-configuring the faulty processor during runtime or bootup.…”

Section: Related Workmentioning

confidence: 99%

A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors

Pan

Rodrigues

Kundu

2015

ACM Trans. Embed. Comput. Syst.

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Device reliability and manufacturability have emerged as dominant concerns in end-of-road CMOS devices. An increasing number of hardware failures are attributed to manufacturability or reliability problems. Maintaining an acceptable manufacturing yield for chips containing tens of billions of transistors with wide variations in device parameters has been identified as a great challenge. Additionally, today’s nanometer scale devices suffer from accelerated aging effects because of the extreme operating temperature and electric fields they are subjected to. Unless addressed in design, aging-related defects can significantly reduce the lifetime of a product. In this article, we investigate a micro-architectural scheme for improving yield and reliability of homogeneous chip multiprocessors (CMPs). The proposed solution involves a hardware framework that enables us to utilize the redundancies inherent in a multicore system to keep the system operational in the face of partial failures. A micro-architectural modification allows a faulty core in a CMP to use another core’s resources to service any instruction that the former cannot execute correctly by itself. This service improves yield and reliability but may cause loss of performance. The target platform for quantitative evaluation of performance under degradation is a dual-core and a quad-core chip multiprocessor with one or more cores sustaining partial failure. Simulation studies indicate that when a large, high-latency, and sparingly used unit such as a floating-point unit fails in a core, correct execution may be sustained through outsourcing with at most a 16% impact on performance for a floating-point intensive application. For applications with moderate floating-point load, the degradation is insignificant. The performance impact may be mitigated even further by judicious selection of the cores to commandeer depending on the current load on each of the candidate cores. The area overhead is also negligible due to resource reuse.

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Section: Related Workmentioning

confidence: 99%

A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors

Pan

Rodrigues

Kundu

2015

ACM Trans. Embed. Comput. Syst.

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“…Redundancy is a commonly used technique for improving lifetime reliability as well as yield of processor systems [1] [6] [13]. When applied to microprocessors, chips can maintain operability in the presence of defects or failures by detecting and isolating, correcting, and/or replacing microarchitecture components reactively on a first-come, first-served basis after components become faulty.…”

Section: Proactive Use Of Redundancymentioning

confidence: 99%

“…Some techniques are based on adjusting the operational characteristics (e.g., supply voltage, frequency, threshold voltage, or duty cycle) to reduce or recover from wearout stress conditions of failure mechanisms [10][12] [22]. Others are based on using some form of redundancy (e.g., component sparing) used reactively to tolerate the effects of wearout [6] [13].…”

Section: Introductionmentioning

confidence: 99%

A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime

Shin

Zyuban

Bose

et al. 2008

2008 International Symposium on Computer Architecture

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Microarchitectural redundancy has been proposed as a means of improving chip lifetime reliability. It is typically used in a reactive way, allowing chips to maintain operability in the presence of failures by detecting and isolating, correcting, and/or replacing components on a first-come, first-served basis only after they become faulty. In this paper, we explore an alternative, more preferred method of exploiting microarchitectural redundancy to enhance chip lifetime reliability. In our proposed approach, redundancy is used proactively to allow non-faulty microarchitecture components to be temporarily deactivated, on a rotating basis, to suspend and/or recover from certain wearout effects. This approach improves chip lifetime reliability by warding off the onset of wearout failures as opposed to reacting to them posteriorly. Applied to on-chip cache SRAM for combating NBTI-induced wearout failure, our proactive wearout recovery approach increases lifetime reliability (measured in mean-time-to-failure) of the cache by about a factor of seven relative to no use of microarchitectural redundancy and a factor of five relative to conventional reactive use of redundancy having similar area overhead.

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“…Error correction codes are much more difficult to implement on latches, since latches are often used individually, or in small groups. Heavy weight microarchitectural techniques such as duplicated or triplicated computation units, time redundant computations, or watchdog processors, are applied in mission critical systems [28], [29], [30], [31]. In non-mission critical systems, derating factors alone may void the need for microarchitectural changes [32].…”

Section: B Ser Simulation Toolmentioning

confidence: 99%

Protecting Big Blue from Rogue Subatomic Particles

Cannon¹,

KleinOsowski

Gordon³

et al. 2007

2007 IEEE International Conference on Integrated Circuit Design and Technology

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Fig. 1. Representative SOI transistor showing the column of charge generated from an a-particle strike. Figure reproduced from [1].Abstract-Device technology scaling continues to deliver faster and smaller transistors, contributing to IBMs continued leadership in Server Systems. However, there is also a dark side to device technology scaling... As transistors shrink, the amount of charge required to change the logic state of a memory or a logic circuit (i.e. flip a 1 to a 0 and vice versa) also shrinks. This complication spurs continued effort at IBM to test, characterize, and mitigate these transient bit flips, so called soft errors. In this paper we survey our ongoing work in this realm and introduce our views on trends for soft errors in future device technologies.

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Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology

Cited by 38 publications

References 5 publications

A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors

A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors

A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime

Protecting Big Blue from Rogue Subatomic Particles

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