Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip

Abstract

MotivationShrinking feature sizes and increasing clock speeds are the most visible signs of the tremendous advances in VLSI design, which will accommodate billions of transistors on a single chip in the near future [12]. This comes at the price of increased system-level complexity, however: With today's deep submicron technology with GHz clock speeds, wiring delays dominate transistor switching delays, and signals cannot traverse the whole die within a single clock cycle any more. Moreover, the reduced voltage swing needed for high clock speeds and low power consumption dramatically increases the adverse effects of single event upsets like α-particle or neutron hits. The resulting increase of the transient failure rate (soft-error rate) [17] and crosstalk sensitivity [23] has raised concerns about the dependabil- ity of future generation VLSI chips [5]. In fact, a modern VLSI chip can no longer be viewed as a monolithic block of synchronous hardware, where all state transitions occur simultaneously. Rather, VLSI chips are nowadays considered as systems of interacting subsystems -the advent of Systems-on-Chip (SoC). Due to the problems listed above, however, SoCs have much in common with the loosely-coupled distributed systems that have been studied by the fault-tolerant distributed algorithms community for decades. This paper explores whether it is possible to utilize some of this research for SoCs and similar VLSI devices.More specifically, in the context of our DARTS-Project (ti.tuwien.ac.at/darts), which is a joint project between Vienna University of Technology and Austrian Aerospace, we will explore an alternative approach (patented in [26]) to synchronous clocking in VLSI chips and PCB-level system designs. As shown in Fig. 1, the idea is to replace the external quartz oscillator and the clock tree, which supplies the clock signal to the different functional units (Fu i ) on a traditional chip, using a GALS-like approach [4]: Every functional unit has attached a dedicated fault-tolerant tick generation block (TS-Alg), which generates the Fu's local clock signal. In contrast to GALS, however, our approach ensures that the local clock signals of different Fu's are closely synchronized to each other. To accomplish this, all TS-Alg blocks communicate with each other over a simple "network" of clock signals (TS-Net). This alternative clock- ing approach has a number of advantages, which makes it particularly promising for certain application domains: First of all, it does not need a quartz oscillator, which is an expensive and sensitive device (shock, vibration, temperature etc.). The generated clock always runs at the maxi-

Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip

“…While the EPs serve as FIFO buffers for clock signal transitions, the DM is responsible for removing transitions that match in both pipelines. Note that we proved in [11] that ℓ − k remains bounded, with a bound that depends on the ratio Θ of the slowest vs. fastest delay of certain critical paths in the system only. Consequently, the pipeline depth and hence the whole design of the TG units is quite independent of the implementation technology.…”

“…As proved in [11], the DARTS clocking scheme guarantees a worst-case synchronization precision π in the range of a few clock ticks; the actual value of π again depends on the ratio Θ. To tolerate up to f Byzantine faulty TG-Algs, a system of n ≥ 3f + 2 TG-Alg nodes is required 2 .…”

“…The key problem solved in DARTS is the implementation of the -originally software based -algorithm in asynchronous digital TG-Algs logic. Apart from substantial adaptations of the original Algorithm 1, this also required refined techniques for proving correctness and analyzing the achievable synchronization precision and clock frequency [11]. Algorithm 1 relies on a fully connected network, atomicity of actions, and the exchange of messages that carry an unbounded integer identifier.…”

“…For example, in [8,9], it has been shown that self-stabilizing algorithms [7], which recover even from massive transient faults, can be employed in VLSI chips. Similarly, in our DARTS 1 project (Distributed Algorithms for Robust Tick-Synchronization), we have implemented a fault-tolerant clocking scheme for SoCs by adapting a simple clock synchronization algorithm to the requirements and constraints of asynchronous digital logic [11].…”

VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation

“…While an in-depth analysis of the formal aspects of the DARTS approach can be found in [33], this paper will be more concerned with the implementation-related issues of DARTS. In particular, throughout the remainder of this section we will investigate the foundations for our concept, namely, the selection of a suitable algorithm and the constraints that have to be considered when implementing that abstract algorithm as VLSI chip design.…”