VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation

Fuchs, Gottfried; Steininger, Andreas

doi:10.1155/2011/936712

Cited by 5 publications

(2 citation statements)

References 39 publications

(45 reference statements)

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“…Moreover, asynchrony is also a quite natural phenomenon at higher system layers, as in Globally Asynchronous, Locally Synchronous (GALS) architectures [5] , for example. Unfortunately, unlike for synchronous systems, fault-tolerance is difficult to guarantee in asynchronous systems [6] , and has hence not received much attention in asynchronous digital circuits [7–10,1,11] .…”

Section: Introductionmentioning

confidence: 99%

An infrastructure for accurate characterization of single-event transients in digital circuits

Veeravalli

Polzer

Schmid

et al. 2013

Microprocessors and Microsystems

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We present the architecture and a detailed pre-fabrication analysis of a digital measurement ASIC facilitating long-term irradiation experiments of basic asynchronous circuits, which also demonstrates the suitability of the general approach for obtaining accurate radiation failure models developed in our FATAL project. Our ASIC design combines radiation targets like Muller C-elements and elastic pipelines as well as standard combinational gates and flip-flops with an elaborate on-chip measurement infrastructure. Major architectural challenges result from the fact that the latter must operate reliably under the same radiation conditions the target circuits are exposed to, without wasting precious die area for a rad-hard design. A measurement architecture based on multiple non-rad-hard counters is used, which we show to be resilient against double faults, as well as many triple and even higher-multiplicity faults. The design evaluation is done by means of comprehensive fault injection experiments, which are based on detailed Spice models of the target circuits in conjunction with a standard double-exponential current injection model for single-event transients (SET). To be as accurate as possible, the parameters of this current model have been aligned with results obtained from 3D device simulation models, which have in turn been validated and calibrated using micro-beam radiation experiments at the GSI in Darmstadt, Germany. For the latter, target circuits instrumented with high-speed sense amplifiers have been used for analog SET recording. Together with a probabilistic analysis of the sustainable particle flow rates, based on a detailed area analysis and experimental cross-section data, we can conclude that the proposed architecture will indeed sustain significant target hit rates, without exceeding the resilience bound of the measurement infrastructure.

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Section: Introductionmentioning

confidence: 99%

An infrastructure for accurate characterization of single-event transients in digital circuits

Veeravalli

Polzer

Schmid

et al. 2013

Microprocessors and Microsystems

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“…The DARTS clocking scheme has been implemented both in an FPGA [20] and in a custom radiation-hardened ASIC [24,27], which proves that the approach is feasible in practice and indeed works very well. Although the implementation complexity of DARTS is definitely not negligible, it must be considered as the price for a fault-tolerant clocking system.…”

Section: Introductionmentioning

confidence: 99%

Reconciling fault-tolerant distributed computing and systems-on-chip

Függer

Schmid

2011

Distrib. Comput.

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Classic distributed computing abstractions do not match well the reality of digital logic gates, which are the elementary building blocks of Systems-on-Chip (SoCs) and other Very Large Scale Integrated (VLSI) circuits: Massively concurrent, continuous computations undermine the concept of sequential processes executing sequences of atomic zerotime computing steps, and very limited computational resources at gate-level make even simple operations prohibitively costly. In this paper, we introduce a modeling and analysis framework based on continuous computations and zerobit message channels, and employ this framework for the correctness & performance analysis of a distributed faulttolerant clocking approach for Systems-on-Chip (SoCs). Starting out from a "classic" distributed Byzantine fault-tolerant tick generation algorithm, we show how to adapt it for direct implementation in clockless digital logic, and rigorously prove its correctness and derive analytic expressions for worst case performance metrics like synchronization precision and clock frequency. Rather than on absolute delay values, both the algorithm's correctness and the achievable synchronization precision depend solely on the ratio of certain path delays. Since these ratios can be mapped directly to placement & routing constraints, there is typically no need This work originates in our DARTS project, which has been a joint effort of Vienna University of Technology and RUAG Space, see http://ti.tuwien.ac.at/darts for details. It has been supported by the Austrian bm:vit FIT-IT project DARTS (809456-SCK/SAI) and the Austrian FWF projects Theta (P17757), PSRTS (P20529) and FATAL (P21694).M. Függer (B) · U. Schmid Technische Universität Wien, Embedded Computing Systems Group (E182/2), Treitlstraße 3, 1040 Vienna, Austria e-mail: fuegger@ecs.tuwien.ac.at U. Schmid e-mail: s@ecs.tuwien.ac.at for changing the algorithm when migrating to a faster implementation technology and/or when using a slightly different layout in an SoC.

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