Very large scale integration (VLSI) technology has evolved to a level where large systems, previously implemented as printed circuit boards with discrete components, are integrated into a single integrated circuit (IC). But aggressive new chip design technologies frequently adversely affect chip reliability during functional operation. Reliability is of critical importance in situations where a computer malfunction could have catastrophic results. Reliability is used to describe systems in which it is not feasible to repair (as in computers on board satellites) or in which the computer is serving a critical function and cannot be lost even for the duration of a replacement (as insight control computers on an aircraft) or in which therepair is prohibitively expensive. The use of concurrent error detection scheme with order to achieve the high reliability requirement of modern computer systems is becoming an important design technique. The present paper describes implementation of error-detection mechanisms for detecting faults within the Arithmetic Logic Unit (ALU). The Boolean unit of the ALU uses duplication of hardware with comparison as the error detection mechanism. The arithmetic unit of the ALU uses residue codes as the error detection mechanisms. If a fault is detected in the ALU we have to replace it with the spare ALU which will make error correction possible. We will compare this fault tolerance mechanism with the current fault-tolerance mechanisms (Triple redundancy with single voting scheme and Triple modular redundancy with triplicated voting mechanism).

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Asynchronous circuits exhibit considerable advantages over their synchronous counterparts, like lower dynamic power and inherent variation tolerance, which makes them increasingly interesting. Their fault-tolerance behavior, however, is not yet fully explored. In particular, temporal masking, as seen with synchronous circuits, seems to be completely nonexistent in asynchronous logic. Instead, there seem to be other masking mechanisms in the control structure that establish an extra barrier for transient fault propagation. In this paper we will explore these masking mechanisms in a qualitative as well as quantitative manner. To this end we first analyze the behavior of a Muller C-element, one fundamental building block in asynchronous designs. In a next step we evaluate the behavior of a chain of these elements, forming a so-called Muller pipeline, the basic control structure of many asynchronous designs, under transient faults. To validate our theoretical findings we inject radiation induced single event transients (SETs) in an extensive simulation campaign. The results show that the SET susceptibility of the Muller pipeline is indeed state dependent. This knowledge can be leveraged to improve, e.g., the radiation hardness of asynchronous circuits by preferring the more robust states in their design wherever possible.