Protecting an Asynchronous NoC against Transient Channel Faults

Naqvi, Syed Rameez; Veeravalli, Varadan Savulimedu; Steininger, Andreas

doi:10.1109/dsd.2012.108

Cited by 6 publications

(2 citation statements)

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“…This implies that the presence of a global clock signal leads to more latency and power consumption. Asynchronous circuits provide an alternate solution for these challenges that arise due to the presence of a global clock [49,55], as the clock signal is replaced by the handshaking (request REQ and acknowledge ACK) signals in such circuits. The datapath becomes active upon the reception of a request signal REQ, and it goes back to the inactive state after it has completed its operation and issued an acknowledge signal ACK.…”

Section: Introductionmentioning

confidence: 99%

Asynchronous Floating-Point Adders and Communication Protocols: A Survey

2020

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Addition is the key operation in digital systems, and floating-point adder (FPA) is frequently used for real number addition because floating-point representation provides a large dynamic range. Most of the existing FPA designs are synchronous and their activities are coordinated by clock signal(s). However, technology scaling has imposed several challenges like clock skew, clock distribution, etc., on synchronous design due to presence of clock signal(s). Asynchronous design is an alternate approach to eliminate these challenges imposed by the clock, as it replaces the global clock with handshaking signals and utilizes a communication protocol to indicate the completion of activities. Bundled data and dual-rail coding are the most common communication protocols used in asynchronous design. All existing asynchronous floating-point adder (AFPA) designs utilize dual-rail coding for completion detection, as it allows the circuit to acknowledge as soon as the computation is done; while bundled data and synchronous designs utilizing single-rail encoding will have to wait for the worst-case delay irrespective of the actual completion time. This paper reviews all the existing AFPA designs and examines the effects of the selected communication protocol on its performance. It also discusses the probable outcome of AFPA designed using protocols other than dual-rail coding.

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Section: Introductionmentioning

confidence: 99%

Asynchronous Floating-Point Adders and Communication Protocols: A Survey

2020

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“…eliminates the need for a clock, and at the same time provides an inherent ability to adapt to uncertainties and even dynamic changes of timing parameters. Lower power dissipation, reduced electromagnetic emission, higher operating speed, and better modularity are among a few other traits associated with asynchronous logic designs [3], [4].…”

Section: Introductionmentioning

confidence: 99%

Towards Designing Asynchronous Microprocessors: From Specification to Tape-Out

et al. 2019

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Proceeding miniaturization in the VLSI circuits continues to pose challenges to the conventionally used synchronous design style in microprocessors. These include the distribution of clock in the GHz range, robustness to delay variations, reduction in electromagnetic interference, and energy conservation, to name a few. The asynchronous logic has been known for its ability to address the aforementioned challenges by means of the closed-loop handshake protocols, instead of notorious clock signals. Because of these advantages, there have been numerous attempts on building general and special purpose microprocessors during the last three decades. Still, however, the number of asynchronous processors commercially available is scarce, mainly due to an insufficient electronic design and automation tools support, an ambiguous design flow and testing mechanisms for asynchronous logic and, most importantly, absence of a forum to look for relevant works, explaining the design steps and tools for such microprocessors. This paper is intended to bridge this gap by 1) reviewing the design principles of asynchronous logic, including classification, signaling conventions, and pipelining approaches; 2) presenting the complete design flow and available electronic design and automation tools; 3) developing an encyclopedia of various general and special purpose microprocessors proposed by far; and 4) presenting an evaluation of those works in terms of area on the die and performance metrics. This paper will also serve as guidelines for the asynchronous microprocessor design and implementation in all phases from specification to tape-out.INDEX TERMS Asynchronous logic, electronic design and automation, microprocessor.

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