Fault tolerant nanoelectronic processor architectures

Abstract

In this paper we propose a fault-tolerant processor architecture and an associated fault-tolerant computation model capable of fault tolerance in the nanoelectronic environment that is characterized by high and time varying fault rates. The proposed fault tolerant processor architecture not only guarantees the correctness of computation but also is flexible in that it dynamically trades-off computation resources and performance. The core of the architecture is a decentralized instruction control unit called the voter that achieves both fault tolerance and the maximum parallel execution of instructions by exploiting the abundant computational resources provided by nanotechnologies. Although the result of each instruction needs to be confirmed by executing it on multiple computation units, multiple unconfirmed instructions can proceed as speculative branches. The voter implements a hardware-frugal computation unit allocation algorithm to organize the redundant computations and to dynamically control the growth of speculative branches.

Architectural-level fault tolerant computation in nanoelectronic processors

“…Hardware resource growth in the speculative computations is controlled so that performance boost does not occur at hardware expense. An instance of the proposed computation model can be found in [18].…”