Fault Tolerant Quadded Logic Cell Structure with Built-in Adaptive Time Redundancy

Schiefer, Philipp; McWilliam, Richard; Purvis, Alan

doi:10.1016/j.procir.2014.07.115

Cited by 9 publications

(4 citation statements)

References 10 publications

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“…A useful perspective is to regard zero-maintenance as a multi-level design problem in similar fashion to the highly integrated nature of electronic systems design. An early analysis Time-shared redundancy [3] x x x [112] x x x [116] x x x ASIC (fine-grained) [82] x x x [117] x x x ASIC, (heterogeneous) [106] x x [118] x x [119] x x x [120] x x x FPGA implementations [99] x x x [121] x x x [122] x x x [123] x x x x…”

Section: B Hierarchical Perspectivementioning

confidence: 99%

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

McWilliam

Khan

Farnsworth

et al. 2018

Microelectronics Reliability

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Self-engineering systems that are capable of repairing themselves in-situ without the need for human decision (or intervention) could be used to achieve zero-maintenance. This philosophy is synonymous to the way in which the human body heals and repairs itself up to a point. This article synthesises issues related to an emerging area of self-healing technologies that links software and hardware mitigations strategies. Efforts are concentrated on built-in detection, masking and active mitigation that comprises self-recovery or self-repair capability, and has a focus on system resilience and recovering from fault events. Design techniques are critically reviewed to clarify the role of fault coverage, resource allocation and fault awareness, set in the context of existing and emerging printable/nanoscale manufacturing processes. The analysis presents new opportunities to form a view on the research required for a successful integration of zero-maintenance. Finally, the potential cost benefits and future trends are enumerated.

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Section: B Hierarchical Perspectivementioning

confidence: 99%

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

McWilliam

Khan

Farnsworth

et al. 2018

Microelectronics Reliability

Self Cite

View full text Add to dashboard Cite

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“…Figure 1 illustrates three examples of fine-grained logic redundancy strategies that have been proposed. Future nanoscale logic will require finegrained design strategies to improve their manufacturing yield, 10 for which quadded logic 11 and temporal redundancy 12 architectures have been proposed. The most prolific strategies for error tolerance in reconfigurable platforms are based on configuration scrubbing.…”

Section: Introductionmentioning

confidence: 99%

“…From left to right: triple modulo redundancy with voter, 10 quadded logic 11 and series/parallel redundancy in CMOS logic. 12 protect data patterns and logic configurations from SEU and MBU by continually refreshing the correct pattern at a fine-grained level. Redundancy is applied in the form of information stored within the elements of a cellular automaton (CA), which, in turn, creates a stable logic configuration that is highly resilient.…”

Section: Introductionmentioning

confidence: 99%

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Creating self-configuring logic with built-in resilience to multiple-upset events

McWilliam

Schiefer

Purvis

2015

Proceedings of the Institution of Mechanical Engineers, Part B:

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Electronic systems are prone to failures, whether during manufacture or throughout their in-service lifetime. A number of design and fabrication techniques are presently employed that maintain an economical production yield. However, the cost of through-life maintenance and fault mitigation operations for complex, high-value systems remains a major challenge and requires new design methods in order to increase their resilience. In this article, the focus is on applications that are sensitive to transient random errors caused by single-event upsets and multiple-bit upsets occurring within their electronic systems and sub-systems, as well as applications that benefit from fault detection and localisation. A novel self-restoration strategy is proposed based on a two-layer design approach comprising a fault-tolerant coordination layer with convergent cellular automata and a configurable functional logic layer. This design strategy is able to self-reconstruct the correct functional logic configuration in the event of transient faults without external intervention. The necessary convergent cellular automata rule set and state table sizes for 3 3 3 and 4 3 4 binary coded patterns are analysed in order to estimate the generic resource requirements for larger designs. Additionally, the possibility of exploiting the design for built-in fault detection and diagnostic reporting is investigated.

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Optical Inspection and Attacks

2012

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Fault Tolerant Quadded Logic Cell Structure with Built-in Adaptive Time Redundancy

Cited by 9 publications

References 10 publications

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

Creating self-configuring logic with built-in resilience to multiple-upset events

Optical Inspection and Attacks

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