Fault tuples in diagnosis of deep-submicron circuits

Blanton, R. D.; Chen, J.T.; Desineni, R.; Dwarakanath, K.N.; Maly, W.; Vogels, Thijs

doi:10.1109/test.2002.1041765

Cited by 40 publications

(13 citation statements)

References 18 publications

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“…If the defect description is not specified, then options must be specified to direct the defect generation process. The supported defect types include: open, resistive via, signal bridge, supply bridge, and various kinds of cell defects that include the "nasty polysilicon defect" [44],…”

Section: Defect Simulationmentioning

confidence: 99%

“…The different options for defect generation will be described in detail in Section 4.3. The supported defect types include: open, resistive via, signal bridge, supply bridge, and various kinds of cell defects that include the "nasty polysilicon defect" [44], transistor stuck-open, and transistor stuck-closed. The test patterns mimic the tester stimulus that would be applied to the circuit during production testing.…”

Section: Framework Flowmentioning

confidence: 99%

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Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Tam¹,

Blanton

2012

IEEE Des. Test. Comput.

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In the integrated circuit (IC) industry, all products must go through three phases before they are available in the market, namely design, manufacturing, and testing. Design, obviously, refers to the process of converting the early concepts of the product into a precise description of its implementation. Manufacturing then uses this description to fabricate the product, where the design is physically materialized onto the silicon wafer and later packaged into the product. If design and manufacturing are perfect, then every fabricated IC is completely functional, thereby obliterating the need for testing. Unfortunately, both design and manufacturing are not ideal; therefore every manufactured IC must be subject to stringent testing procedures to ensure that most bad ICs are identified and prevented from shipping to the end-users.ICs are deemed bad when they contain certain defects that cause the ICs to fail the specifications.Defects are unintended structural and/or material changes of the IC due to design/manufacturing imperfections.These physical changes may alter the electrical characteristics of the circuit, which are sometimes severe enough to lead to a failure (i.e., violation of one or more design specifications). Common defects in IC manufacturing can be caused by contaminations in the process, variations of the process conditions, or simply the difficulty to fabricate certain features of the design. The last issue is the focus of this dissertation. Defects that arise due to certain aspects of the design being sensitive to the manufacturing process with an elevated likelihood of failure are known as systematic defects. This dissertation addresses the issues related to the prevention and identification of systematic defects by analyzing a large amount of manufactured ICs that have failed testing.For systematic-defect prevention, one common approach is to use design-for-manufacturability (DFM) rules to communicate hard-to-manufacture features to designers so that these features can be minimized in the iii design. Obviously, different rules describe different features and thus their violation/adherence will have different impact on the manufacturability of the product. It is therefore desirable to measure the relative importance of the rules and how they affect product yield. To address this issue, a method called RADAR (Rule Assessment of Defect-Affected Regions) has been developed for measuring the effectiveness of DFM rules in preventing systematic defects. RADAR analyzes a large amount of test data of failed ICs to draw statistical conclusion.Taking preventive measures, such as enforcing DFM rules, is necessary to ensure sufficient product yield. Unfortunately, the amount of resource (circuit area, designer's time, etc.) dedicated to DFM can be quite limited. It is therefore impractical to anticipate and prevent every possible hard-to-manufacture design features before the product is manufactured. Thus, systematic defects can still exist. Therefore, a mechanism is required to identify systematic ...

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Section: Defect Simulationmentioning

confidence: 99%

Section: Framework Flowmentioning

confidence: 99%

Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Tam¹,

Blanton

2012

IEEE Des. Test. Comput.

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“…In [4], a flipped-scan was introduced by adding inverters along the scan path so as to make it difficult for hackers to discover the internal scan structure at the cost of small hardware overhead; however, it cannot protect the circuit under test (CUT) from the scan-based attacks as presented in [2] and [3]. In [5], Agrawal et al discussed the security threat of flipped-scan [4] by introducing a simple reset-based SSCA, and then developed a XOR-chain structure…”

Section: Introductionmentioning

confidence: 99%

Resolution of Diagnosis Based on Transition Faults

Pomeranz

Reddy

2012

IEEE Trans. VLSI Syst.

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The conventional detection conditions for transition faults do not predict fault effects that may be created when transition faults are activated and/or propagated by pulses (or hazards). For this, detection conditions that take hazards into consideration need to be used. However, since the occurrence of pulses cannot be predicted accurately based on a gatelevel circuit description, the transition fault model becomes more susceptible to pattern-dependent effects, where errors on observed outputs that are predicted by the fault model may not appear in a circuit-under-diagnosis. This paper considers the implications of these pattern-dependent effects on the resolution of fault diagnosis based on transition faults.

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“…Recently, much evidence shows that simple fault models such as permanent stuck-at faults are not adequate for diagnosis [Blanton et al 2002;Sato et al 2002;Bhatti and Blanton 2006]. For example, there could be a bridging defect between a flip-flop and a logic cell , and thereby leading to a hard-to-diagnose intermittent fault, because this defect may cause a faulty value at the victim flip-flop at some time, and faulty signals in the core logic at some other time.…”

Section: Introductionmentioning

confidence: 99%

A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques

Tzeng

Yang

Huang

2008

ACM Trans. Des. Autom. Electron. Syst.

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Scan chains are popularly used as the channels for silicon testing and debugging. However, they have also been identified as one of the culprits of silicon failure more recently. To cope with this problem, several scan chain diagnosis approaches have been proposed in the past. The existing methods, however, suffer from one common drawback-that is, they rely on fault models and matching heuristics to locate the faults. Such a paradigm may run into difficulty when the fault under diagnosis does not match the fault model exactly, for example, when there is a bridging between a flip-flop and a logic cell, or the fault is temporal and only manifests itself intermittently. In light of this, we propose in this article a more versatile model-free paradigm for locating the faulty flip-flops in a scan chain, incorporating a number of signal processing techniques, such as filtering and edge detection. These techniques performed on the test responses of the failing chip under diagnosis directly can effectively reveal the fault location(s) in a scan chain. As compared to the previous works, our approach is better capable of handling intermittent faults and bridging faults, even under nonideal conditions, for example, when the core logic is also faulty. Experimental results on several real designs indicate that this approach can indeed catch some nasty faults that previous methods could not catch.

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Fault tuples in diagnosis of deep-submicron circuits

Cited by 40 publications

References 18 publications

Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Resolution of Diagnosis Based on Transition Faults

A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques

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