Feature extraction based built-in alternate test of RF components using a noise reference

Akbay, S.S.; Chatterjee, Abhijit

doi:10.1109/vtest.2004.1299254

Cited by 34 publications

(21 citation statements)

References 20 publications

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“…There are still 19 problematic samples which cannot be identified with these schemes. One possible solution is to study their oscillations with variable sampling windows, similar to wavelet analysis as in [14], we did not investigate this solution for the sake of simplicity. The reader should keep in mind that these problematic instances were a result of faulty design process, a well-designed mixer does not show this kind of behavior, and otherwise the yield of the product would be extremely poor.…”

Section: Implementation Examplesmentioning

confidence: 99%

Testing RF Components with Supply Current Signatures

Akbay

Sen

Chatterjee

2007

16th Asian Test Symposium (ATS 2007)

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We propose a technique for low-cost testing of radio-frequency components integrating current signatures and alternate test methodology. The technique is suitable for non-invasive built-in test as well as low-cost automated test equipment (ATE) applications. Main features of the technique are (1) minimum loading on signal path by sampling supply current, (2) flexible test stimulus generation based on system constraints, (3) test time reduction by using a single test stimulus and data acquisition, and (4) accurate prediction of all specification values from the single excitation. Two experiments using the proposed implementation demonstrate the accuracy and efficiency of the technique on both single-balanced and double-balanced mixers built with two different technologies.

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Section: Implementation Examplesmentioning

confidence: 99%

Testing RF Components with Supply Current Signatures

Akbay

Sen

Chatterjee

2007

16th Asian Test Symposium (ATS 2007)

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“…Test compaction methods reduce testing time at a cost of increasing DPPM; defect escapes occur due to skipping the tests that are unlikely to fail but have a nonzero fail probability. Another form of test compaction is to use a set of alternate measurements [4], [5] or using dedicated built-inself-test circuitry that indirectly decides on the pass/fail status of the device [6], [7]. For these techniques, defect escapes occur due to imperfections in the modeling/mapping functions.…”

Section: Introductionmentioning

confidence: 99%

Fast and Accurate DPPM Computation Using Model Based Filtering

Yılmaz

Ozev

2011

2011 Sixteenth IEEE European Test Symposium

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Defective Parts Per Million (DPPM) is an important quality metric that indicates the ratio of defective devices shipped to the customers. It is necessary to estimate and minimize DPPM in order to meet the desired level of quality. However, DPPM estimation requires statistical simulations, which are computationally costly if traditional methods are used. In this work, we propose an efficient DPPM estimation method for analog circuits that greatly reduces the computational burden. We employ a model based approach to selectively simulate only consequential samples in DPPM estimation. We include methods to mitigate the effect of model imperfection and robust model fitting to guarantee a consistent and efficient estimation. Experimental results show that the proposed method achieves 10x to 25x reduction in the number of simulations for an RF receiver front-end circuit.

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“…However, when considering RFIC testing, some issues need to be taken into account such as powerful ADC & DAC, area overhead issue for embedding, power consumption, etc. Presently, some advanced works to develop efficient testing techniques for the RF systems and individually building blocks have been carried out [5][6][7][8][9]. Recent efforts for RF circuit testing have focused on the design of on-chip embedded detectors, or sensors, where the output signals can be tested easily [5,[7][8], and on the methodologies and algorithms for automated test design [6,9].…”

Section: Introductionmentioning

confidence: 99%

“…Presently, some advanced works to develop efficient testing techniques for the RF systems and individually building blocks have been carried out [5][6][7][8][9]. Recent efforts for RF circuit testing have focused on the design of on-chip embedded detectors, or sensors, where the output signals can be tested easily [5,[7][8], and on the methodologies and algorithms for automated test design [6,9]. Instead of testing the devices specifically for performance metrics, the outputs of the detectors were used to estimate the target test specs when the Circuit-UnderTest (CUT) was stimulated.…”

Section: Introductionmentioning

confidence: 99%

An Embedded Rectifier-Based Built-In-Test Circuit for CMOS RF Circuits

Zhang

Farrell

2006

2006 13th IEEE International Conference on Electronics, Circuits and Systems

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Abstract-Built-In-Test (BIT) for Radio Frequency Integrated Circuits (RFIC) is an effective method to reduce the testing cost, especially with the increase of integration level and operating frequency. In this work, a fully integrated CMOS BIT methodology is proposed. The BIT circuit used is rectifierbased and gate-source connected MOS transistor with Substrate Positively-Biased (SPB) scheme is used to further improve the detecting sensitivity. With little current consumption, high input impedance and high frequency scalability this circuit can predict complex high frequency performances of RF circuits such as gain, operating frequency, bandwidth and linearity. Besides, the influence of Process, supply Voltage, and Temperature (PVT) variations on the performance of RF circuits can also be monitored by using this BIT circuit.

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Feature extraction based built-in alternate test of RF components using a noise reference

Cited by 34 publications

References 20 publications

Testing RF Components with Supply Current Signatures

Testing RF Components with Supply Current Signatures

Fast and Accurate DPPM Computation Using Model Based Filtering

An Embedded Rectifier-Based Built-In-Test Circuit for CMOS RF Circuits

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