There are mainly two factors responsible for rapidly escalating production test costs of today's RF and high-speed analog circuits: 1) the high cost of high-speed and RF automatic test equipments and 2) long test times required by elaborate performance tests. In this paper, we propose a low-cost signature test methodology for accelerated production testing of analog and RF integrated circuits. As opposed to prior work, the key contribution of this paper is a new test generation algorithm that directly tracks the ability of input test waveforms to predict the test specification values from the observed test response, even in the presence of measurement noise. The response of the device-under-test (DUT) is used as a "signature" from which all of the performance specifications are predicted. The applied test stimulus is optimized in such a way that the error between the measured DUT performances and the predicted DUT performances is minimized. While existing low-cost test approaches have only been applied to lowand medium-frequency analog circuits, the proposed methodology extends low-cost signature testing to RF integrated circuits by incorporating modulation of a baseband test stimulus and subsequent demodulation of the obtained response to obtain the DUT signature. The proposed low-cost solution can be easily built into a load board that can be interfaced to an inexpensive tester.

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This paper summarizes an alternate test methodology that enables significant reduction in testing time and tester complexity for RF circuits without the need for low-level simulation models. Traditionally, alternate test makes use of circuit and process-level models to analyze the sensitivity of datasheet specifications to the variations in process parameters. In this paper, we demonstrate a "gray-box" approach by creating a high-level simulation model from datasheet information and simple hardware measurements. This model is used together with a customized behavioral simulator to enable efficient search of an alternate test stimulus that is optimal in terms of tester constraints, test time and specification prediction accuracy. The specific example is a third party RF front-end chip, for which 13 specifications including S-parameters, intermodulation products and noise figures are measured with both conventional and alternate methods. The results are compared in terms of testing time, tester cost and accuracy.

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