Fetch directed instruction prefetching

Reinman, Glenn; Calder, Brad; Austin, Todd

doi:10.1109/micro.1999.809439

Cited by 78 publications

(110 citation statements)

References 14 publications

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“…Doing so necessitates predicting the instructions that are likely to be fetched and proactively fetching the corresponding instruction blocks from the lower levels of the cache hierarchy into the L1-I (or prefetch buffers). To that end, fetch-directed prefetching (FDP) [32] decouples the branch predictor from the L1-I and lets the branch predictor run ahead to explore the future control flow. The instruction blocks that are not present in the L1-I along the predicted path are prefetched into the L1-I.…”

Section: Conventional Instruction-supply Pathmentioning

confidence: 99%

Confluence

Kaynak¹,

Grot

Falsafi³

2015

Proceedings of the 48th International Symposium on Microarchitecture

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Multi-megabyte instruction working sets of server workloads defy the capacities of latency-critical instructionsupply components of a core; the instruction cache (L1-I) and the branch target buffer (BTB). Recent work has proposed dedicated prefetching techniques aimed separately at L1-I and BTB, resulting in high metadata costs and/or only modest performance improvements due to the complex control-flow histories required to effectively fill the two components ahead of the core's fetch stream.This work makes the observation that the metadata for both the L1-I and BTB prefetchers require essentially identical information; the control-flow history. While the L1-I prefetcher necessitates the history at block granularity, the BTB requires knowledge of individual branches inside each block. To eliminate redundant metadata and multiple prefetchers, we introduce Confluence -a frontend design with unified metadata for prefetching into both L1-I and BTB, whose contents are synchronized. Confluence leverages a stream-based prefetcher to proactively fill both components ahead of the core's fetch stream. The prefetcher maintains the control-flow history at block granularity and for each instruction block brought into the L1-I, eagerly inserts the set of branch targets contained in the block into the BTB. Confluence provides 85% of the performance improvement provided by an ideal frontend (with a perfect L1-I and BTB) with 1% area overhead per core, while the highest-performance alternative delivers only 62% of the ideal performance improvement with a per-core area overhead of 8%.

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Section: Conventional Instruction-supply Pathmentioning

confidence: 99%

Confluence

Kaynak¹,

Grot

Falsafi³

2015

Proceedings of the 48th International Symposium on Microarchitecture

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“…First, most of these techniques suffer in the presence of program branches. While there are some prefetch techniques that handle branches using dynamic prediction [3,17], those methods can not be used effectively in embedded systems employing CPU cores since they require access to information deep in the processor core that may not be exposed outside the core (e.g., branch prediction tables, branch history tables, or pipeline state). Moreover, the unpredictable instruction flow behavior of embedded networking leads to many context switches and interrupt vectoring, again rendering prefetching less effective.…”

Section: Related Workmentioning

confidence: 99%

Cluster miss prediction for instruction caches in embedded networking applications

Batcher

Walker

2004

Proceedings of the 14th ACM Great Lakes Symposium on VLSI

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In this paper, we describe a new method of instruction prefetching that reduces the cache miss penalty by anticipating the cache behavior based on previous execution. Our observations indicate that instruction cache misses often repeat in clusters under certain conditions prevalent in real time embedded networking systems. By identifying the start of a cluster miss sequence and preparing an instruction buffer for the upcoming cache misses, the miss penalty can be reduced if a miss does occur. A sample industrial networking example is used to illustrate the effectiveness of this technique compared with other prefetch methods.

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“…Software prefetching relies on the compiler to perform static program analysis and to selectively insert prefetch instructions into the executable code [16][17][18][19]. Hardware-based prefetching, on the other hand, requires no compiler support, but it does require some additional hardware connected to the cache [8][9][10][11][12][13][14][15]. This type of prefetching is designed to be transparent to the processor.…”

Section: Related Workmentioning

confidence: 99%

“…While several other prefetching schemes have been proposed, such as adaptive sequential prefetching [11], prefetching with arbitrary strides [11,14], fetch directed prefetching [13], and selective prefetching [15], Pierce and Mudge [20] have proposed a scheme called wrong path instruction prefetching. This mechanism combines next-line prefetching with the prefetching of all instructions that are the targets of branch instructions regardless of the predicted direction of conditional branches.…”

Section: Related Workmentioning

confidence: 99%

“…Several methods have been proposed to exploit more instruction-level parallelism in superscalar processors and to hide the latency of the main memory accesses, including speculative execution [1][2][3][4][5][6][7] and data prefetching [8][9][10][11][12][13][14][15][16][17][18][19][20][21]. To achieve high issue rates, instructions must be fetched beyond the basic block-ending conditional branches.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions

Sendag

Lilja

Kunkel³

2002

Euro-Par 2002 Parallel Processing

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Abstract.As the degree of instruction-level parallelism in superscalar architectures increases, the gap between processor and memory performance continues to grow requiring more aggressive techniques to increase the performance of the memory system. We propose a new technique, which is based on the wrong-path execution of loads far beyond instruction fetch-limiting conditional branches, to exploit more instruction-level parallelism by reducing the impact of memory delays. We examine the effects of the execution of loads down the wrong branch path on the performance of an aggressive issue processor. We find that, by continuing to execute the loads issued in the mispredicted path, even after the branch is resolved, we can actually reduce the cache misses observed on the correctly executed path. This wrong-path execution of loads can result in a speedup of up to 5% due to an indirect prefetching effect that brings data or instruction blocks into the cache for instructions subsequently issued on the correctly predicted path. However, it also can increase the amount of memory traffic and can pollute the cache. We propose the Wrong Path Cache (WPC) to eliminate the cache pollution caused by the execution of loads down mispredicted branch paths. For the configurations tested, fetching the results of wrong path loads into a fully associative 8-entry WPC can result in a 12% to 39% reduction in L1 data cache misses and in a speedup of up to 37%, with an average speedup of 9%, over the baseline processor.

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Fetch directed instruction prefetching

Cited by 78 publications

References 14 publications

Confluence

Confluence

Cluster miss prediction for instruction caches in embedded networking applications

Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions

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