Field Effect Diode (FED): A novel device for ESD protection in deep sub-micron SOI technologies

Steep Subthreshold Swing n- and p-Channel Operation of Bendable Feedback Field-Effect Transistors with p+–i–n+ Nanowires by Dual-Top-Gate Voltage Modulation

“…The abrupt increase in the diode current corresponds to the "latch-up" phenomenon, which has also been observed in biristors, 27,28 thyristors, 29 and field-effect diodes. 30 In our NW FBFETs, the generation of a positive feedback loop triggers the latch-up phenomenon. Figure 2c uses energy band diagrams to illustrate the positive feedback loop in the NW FBFET that generates latch-up as V DS increases.…”

SOI FED-SRAM Cell: Structure and Operation

“…Here, the p-n junctions sandwiched between the anode and the cathode are gate-induced, rather than built-in (doped-in), and thus, there is no need for precise control of the film doping profile, and the nearly intrinsic SOI film has higher carrier lifetime, and improves the state 1 retention (i.e., t rest ). Although a somewhat relaxed geometry FED was used here for proof of concept purposes, our previous results [10], [11], [17] suggest that it should be possible to design FED memory cells of superior scalability and performance: the gap length between gates G1 and G2 can be shrunk down to the technological limit without affecting the FED properties very much [18]. In fact, it is possible to push scaling even further (down to the 20-nm node according to our simulations [19]) using advanced FEDs, such as double-gate (DG), gate-all-around (GAA), and other multigate (MuG) structures, where the gate control of the channel is stronger.…”

“…Although similar to TCCT, the FED structure offers unique advantages, deriving from the induced rather than the built-in nature of the FED thyristor. We have previously used the FED for electrostaticdischarge protection of SOI CMOS chips, and discussed its design and operation in detail [10], [11]. We have also recently designed and analyzed an FED-based DRAM-like memory cell [12].…”

Gate-controlled field-effect diodes and silicon-controlled rectifier for charged-device model ESD protection in advanced SOI technology

“…However, the original FED DC current anode turn-on voltage (V on ) is below the supply voltage (V dd ) [24], which translates into a high level of leakage current under normal conditions, unless a high gate bias (>2 V) is applied to keep the P-N-P-N structure. Such a gate bias source is usually not readily available on-chip.…”

“…3) and the field-effect diode (FED) (Fig. 4) were developed [23][24][25] based on the structures proposed in [26][27][28]. These devices combine the features of a P-N-P-N SCR to block leakage current during normal operating conditions, with a forward-biased P-N junction diode to shunt high current rapidly during ESD.…”