SOI FED-SRAM Cell: Structure and Operation

Badwan, Ahmad Z.; Chbili, Z.; Li, Qiliang; Ioannou, D.E.

doi:10.1109/ted.2015.2450693

Cited by 23 publications

(7 citation statements)

References 18 publications

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“…Moreover, a thyristor-based RAM and a field-effect diode with two front gates, which are operated by a similar positive feedback loop, have been proposed for SRAM applications 24–28 . For the positive feedback loop generated by weak impact ionization, capacitorless DRAM functionalities have been reported in recent years 29,30 .…”

Section: Introductionmentioning

confidence: 99%

Memory characteristics of silicon nanowire transistors generated by weak impact ionization

Lim

Kim

2017

Sci Rep

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In this study, we demonstrate the static random access memory (SRAM) characteristics generated by weak impact ionization in bendable field-effect transistors (FETs) with n+-p-n+ silicon nanowire (SiNW) channels. Our bendable SiNW FETs show not only superior switching characteristics such as an on/off current ratio of ~105 and steep subthreshold swing (~5 mV/dec) but also reliable SRAM characteristics. The SRAM characteristics originate from the positive feedback loops in the SiNW FETs generated by weak impact ionization. This paper describes in detail the operating mechanism of our device and demonstrates the potential of bendable SiNW FETs for future SRAM applications.

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Section: Introductionmentioning

confidence: 99%

Memory characteristics of silicon nanowire transistors generated by weak impact ionization

Lim

Kim

2017

Sci Rep

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“…As shown in Figure 2a, when V DS is swept from −0.1 to 4.1 V and then back to −0.1 V as a function of V G1 and V G2 , our transistor shows bistable I DS -V DS characteristics owing to the similar structures of thin capacitively-coupled thyristor (TCCT) devices [19][20][21] and field-effect diodes. [22,23] Without gate bias voltages, the transistor exhibits ordinary p-n diode characteristics;…”

Section: Resultsmentioning

confidence: 99%

“…Our switchable-memory transistor is strikingly different from TCCT devices from the viewpoint of the memory-operating domain, which can be modulated by three variables: V G1 , V G2 , and V DS (see Supporting Information). A TCCT structurebased RAM, [19] the field-effect diode, [22,23] and the Z 2 -FET [21] are essentially different from our switchable-memory transistor, which should operate in the I D -V G domain. There are two operation modes in our transistor: the n-channel mode (as a function of V G1 ) and the p-channel mode (as a function of V G2 ).…”

Section: Introductionmentioning

confidence: 99%

Switchable‐Memory Operation of Silicon Nanowire Transistor

Kim

Cho

Lim

et al. 2018

Adv Elect Materials

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of conventional memory are advantages of SRAM and DRAM over new alternatives. Therefore, they will retain their mainstream position in the memory industry for the foreseeable future. Technologies have been proposed to solve the aforementioned limitations of traditional memory devices, such as removing the storage capacitor of DRAM [16,17] and reducing the number of transistors of SRAM. [18] In this study, we demonstrate a switchable-memory transistor with a p + -i-n + doped silicon nanowire whose fabrication process is fully compatible with silicon-based complementary metal-oxide semiconductor (CMOS) technology. The outstanding memory characteristics originate from the positive feedback loop in the intrinsic channel. Notably, our single device not only reduces the number of transistors (constituting a single SRAM cell) in the memory device but also operates the switching function. This is one of the novel strengths of our switchable-memory device for future electronics, as conventional memory devices only provide the function of data storage. The decrease in the number of transistors and the operation of multiple functions can be beneficial for scaling the memory device with regard to the total chip size and power consumption. Hence, we propose a feedback field-effect transistor (FET) with a dual top-gated silicon nanowire channel to enable the switching and memory functions in a single transistor. Results and DiscussionWe demonstrate the switchable-memory characteristics of a silicon nanowire transistor with a dual-gate structure. Figure 1 shows schematic and optical images of our transistor, which consists of a silicon nanowire channel and dual-gate electrodes. On the upper side of the channel region (6 µm long), two gate electrodes (each 2 µm wide) are arranged side by side. The gate electrode located near the p + doped region is named "Gate1 (V G1 )," and the other gate electrode located near the n + doped region is named "Gate2 (V G2 )." Details regarding the fabrication are presented in Experimental Section. Our switchable-memory transistor can be fabricated using conventional CMOS technology, which is clearly advantageous for industrial applications.As shown in Figure 2a, when V DS is swept from −0.1 to 4.1 V and then back to −0.1 V as a function of V G1 and V G2 , our transistor shows bistable I DS -V DS characteristics owing to the similar structures of thin capacitively-coupled thyristor (TCCT) devices [19][20][21] and field-effect diodes. [22,23] Without gate bias voltages, the transistor exhibits ordinary p-n diode characteristics;The switchable-memory operation of a feedback silicon nanowire transistor with a dual-gate structure is demonstrated. The single transistor exhibits volatile memory characteristics with a retention time longer than 3600 s, as well as a switching capability with a subthreshold swing lower than 7 mV dec −1 . A gate-controlled memory window forms around a gate voltage of 0 V owing to the positive feedback loop in the channel region, allowing a program/erase endurance of more th...

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“…Also, the I ON /I OFF ratio of FED is an order of a magnitude larger than a comparable regular MOSFET [2][3][4]. The FED is an attractive device used to design various digital and analogue circuits such as high-speed logic gates [4,5], SRAM and DRAM memory cells [6][7][8][9][10][11], programmable negative resistance circuit [12], high-speed comparator [13], variable gain amplifier [14,15], and electrostatic discharge (ESD) protection circuit [16][17][18]. As the regular FED cannot work properly at nanoscale length, modified versions of FED are proposed to achieve proper I ON /I OFF ratio at channel lengths below 100 nm [2,3,19].…”

Section: Introductionmentioning

confidence: 99%

Improved nanoscale field effect diode

Sheikhian

Sharafi

2019

IET Circuits, Devices & Systems

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To overcome the short channel effects of a regular field effect diode (FED), this paper proposes a novel nanoscale FED. The novel FED has a simple structure that can be fabricated by the standard CMOS process technology. Both regular and novel FEDs are simulated using TCAD tools as a semiconductor drift-diffusion solver. Simulation results show that the novel device can operate properly at nanoscale channel length. The I ON /I OFF ratio of the novel FED is several orders of magnitude higher than of the regular FED.

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SOI FED-SRAM Cell: Structure and Operation

Cited by 23 publications

References 18 publications

Memory characteristics of silicon nanowire transistors generated by weak impact ionization

Memory characteristics of silicon nanowire transistors generated by weak impact ionization

Switchable‐Memory Operation of Silicon Nanowire Transistor

Improved nanoscale field effect diode

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