Field Guide to Optical Lithography

Study of etching bias modeling and correction strategies for compensation of patterning process effects

“…L min = 25 nm, J = 20, d = 0.25 nm, and a = 1.9 nm (i.e. 5% of the minimum CD [19]) are used for investigating the performance of the two correction strategies on the first metal layer of a large standard logic cell (i.e. the MUX4X1 cell with an area of 3.344 Â 1.444 lm 2 ).…”

Closed-loop modeling of silicon nanophotonics from design to fabrication and back again

“…These projection systems consist of complex lens combinations, but they typically adhere to a so-called Kohler setup, shown in Fig. 2 where the pupil (the element constraining the numerical aperture of the system) of the entire lens system is located in the fourier plane of the mask image Mack (2006); Levinson (2001). This allows us to make abstraction of the lens system and the source and approximate the entire projection process using Fourier optics Kintner (1978).…”

Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond

“…The industry is currently stuck with the 193nm optical lithography as the dominant integrated circuit manufacturing process, which is likely to remain so for at least another 5 years. Therefore, it is expected to use 193nm optical lithography for 32nm or even 22nm technology nodes, with the adoption of immersion lithography [3] and advanced resolution enhancement techniques (RET) [4]- [6]. There are other important manufacturing/process challenges, such as topography variations due to chemical-mechanical polishing (CMP), random defects due to missing/extra material, via void/failure, etc., all resulting in additional yield loss (including functional and parametric losses).…”