Fighting stochastic variability in a D‐type flip‐flop with transistor‐level reconfiguration

Abstract

In this study, the authors present a design optimisation case study of D-type flip-flop timing characteristics that are degraded as a result of intrinsic stochastic variability in a 25 nm technology process. What makes this work unique is that the design is mapped onto a multi-reconfigurable architecture, which is, like a field programmable gate array (FPGA), configurable at the gate level but can then be optimised using transistor level configuration options that are additionally built into the architecture. While a hardware VLSI prototype of this architecture is currently being fabricated, the results presented here are obtained from a virtual prototype implemented in SPICE using statistically enhanced 25 nm high performance metal gate MOSFET compact models from gold standard simulations for pre-fabrication verification. A Dtype flip-flop is chosen as a benchmark in this study, and it is shown that timing characteristics that are degraded because of stochastic variability can be recovered and improved. This study highlights significant potential of the programmable analogue and digital array architecture to represent a next-generation FPGA architecture that can recover yield using post-fabrication transistor-level optimisation in addition to adjusting the operating point of mapped designs.

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

“…At the sub-system level, online fault discrimination and monitoring operates at the modular level and within maintenance-heavy products, such as land, air and space vehicles, it becomes possible to monitor component aging via key response factors that that are expected to degrade more progressively over time [2]. These methods focus on self-correction of stuckat faults within nanoscale logic units, for which there are two reasons to consider fine-grained redundancy: firstly, fabrication processes are more prone to defect and variability [63] and the high density of nanoscale manufacturing exacerbates the challenge of high volume production. Secondly, the reduced device dimensions will result in increased susceptibility to inservice faults.…”

Hierarchical Strategies for Efficient Fault Recovery on the Reconfigurable PAnDA Device

“…(iii) Multi-granularity allows faults to be addressed and mitigated with the best cost/benefit tradeoff, and exploiting symmetries of the architecture offers "fault-blind" repair capability by considering functionally equivalent but structurally different alternative mappings. We have previously shown that PAnDA can be used to provide increased circuit performance while simultaneously reducing the effects of variability using SPICE-level architecture simulation [19], [20]. Hierarchical strategies for fault tolerance in reconfigurable architectures, using PAnDA as a suitable candidate, is the subject of this work.…”

“…In this work, we combine a bespoke bio-inspired multireconfigurable FPGA architecture [19], [20], [21]-the programmable analogue and digital array (PAnDA)-with novel "fault blind" circuit repair strategies taking inspiration from dynamic partial reconfiguration and configuration bit string permutation. In this case, "fault blind" refers to the proposed method's ability to repair faults without requiring information of the exact nature or location of a fault.…”

A Synthesizable Memory Grid using BRAMs and Function Generators to Enhance Throughput Efficiency in Regular Expression Pattern Matching Circuits

“…While implementing NFAs as logic, it was observed that if all the source input Flip-Flops (FFs) [10] to the destination input FFs are on -transitions (epsilon transition), then the FFs can be eliminated [8]. This means that epsilon transitions need not be implemented at all, thereby saving more memory logic circuits.…”