Fin Doping by Hot Implant for 14nm FinFET Technology and Beyond

Wood, Bingxi; Khaja, Fareen Adeni; Colombeau, B.; Sun, Shiyu; Waite, Andrew; Jin, Miao; Chen, Hao; Chan, Osbert; Thanigaivelan, Thirumal; Pradhan, N.; Gossmann, Hans‐Joachim L.; Sharma, Shashank; Chavva, Venkataramana; Cai, Man-Ping; Okazaki, Motoya; Munnangi, Samuel Swaroop; Ni, Chi-Nung; Suen, Wesley; Chang, Chorng‐Ping; Mayur, A. J.; Variam, N.; Brand, A.

doi:10.1149/05809.0249ecst

Cited by 24 publications

(16 citation statements)

References 7 publications

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“…Fig. 23 depicts the implant induced damage and proposes to use hot implant as the potential solution 84,85 . …”

Section: Fin Dopant Implantationmentioning

confidence: 99%

“…46(b)) 102 . Additionally, ion implantation can lead to full amorphization of the fin and problematic recrystallization, resulting in defect formation and poor activation of the dopants 85 . Several alternative doping techniques have been investigated to overcome this issue: hot implantation 101 , plasma doping 103 , vapor phase deposition 104 , and solution-based monolayer doping 105,106 are examples.…”

Section: Challenges In Source Drain Contact Formationmentioning

confidence: 99%

“…Hot implant (I/I-HOT) has been developed and shown to eliminate implant damage in the narrow fins of SOI and bulk Si finFETs 84,85 [see Fig. 23].…”

Section: (A) (B)mentioning

confidence: 99%

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Scaling Challenges for Advanced CMOS Devices

Jacob

Xie

Sung

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

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The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

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“…Fig. 23 depicts the implant induced damage and proposes to use hot implant as the potential solution 84,85 . …”

Section: Fin Dopant Implantationmentioning

confidence: 99%

Section: Challenges In Source Drain Contact Formationmentioning

confidence: 99%

See 1 more Smart Citation

Scaling Challenges for Advanced CMOS Devices

Jacob

Xie

Sung

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

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“…By using this method, B. Wood et al demonstrated a half magnitude improvement in fin line conductance and one magnitude in junction leakage for n-type source and drain extension (NSDE) doping compared to a room-temperature implant [120].…”

Section: Damage Controlmentioning

confidence: 99%

The Challenges of Advanced CMOS Process from 2D to 3D

Radamson

Zhang

et al. 2017

Applied Sciences

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Abstract:The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

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“…The socalled heated, raised or hot ion implantation is performed at an elevated temperature to enhance dynamic annealing avoiding damage accumulation. Hot ion implantation has been widely studied in the past [146] and has been applied for the source/drain (S/D) extension formation of Si-channel CMOS FinFETs [147][148][149]. Recently, hot ion implantation has been proved to enhance the performance of SOI CMOS FinFETs, resulting in better on/off characteristics and lower threshold voltage variability [150].…”

mentioning

confidence: 99%

Improved physical models for advanced silicon device processing

Pelaz

Marqués

Aboy

et al. 2017

Materials Science in Semiconductor Processing

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We review atomistic modeling approaches for issues related to ion implantation and annealing in advanced device processing. We describe how models have been upgraded to capture physical mechanisms in more detail as a response to the accuracy demanded in modern process and device modeling. Implantation and damage models based on the binary collision approximation have been improved to describe the direct formation of amorphous pockets for heavy or molecular ions. The use of amorphizing implants followed by solid phase epitaxial regrowth has motivated the development of detailed models that account for amorphization and recrystallization, considering the influence of crystal orientation and stress conditions. We apply simulations to describe the role of implant parameters to minimize residual damage, and we address doping issues that arise in non-planar structures such as FinFETs.

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Fin Doping by Hot Implant for 14nm FinFET Technology and Beyond

Cited by 24 publications

References 7 publications

Scaling Challenges for Advanced CMOS Devices

Scaling Challenges for Advanced CMOS Devices

The Challenges of Advanced CMOS Process from 2D to 3D

Improved physical models for advanced silicon device processing

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