Finding Bounded Path in Graph Using SMT for Automatic Clock Routing

Abstract

Automating the routing process is essential for the semiconductor industry to reduce time-to-market and increase productivity. This study sprang from the need to automate the following critical task in clock routing: given a set of nets, each net consisting of a driver and a receiver, connect each driver to its receiver, where the delay should be almost the same across the nets. We demonstrate that this problem can be reduced to bounded-path, that is, the NP-hard problem of finding a simple path, whose cost is bounded by a given range, connecting two given vertices in an undirected positively weighted graph. Furthermore, we show that bounded-path can be reduced to bit-vector reasoning and solved with a SAT-based bit-vector SMT solver. In order to render our solution scalable, we override the SAT solver's decision strategy with a novel graph-aware strategy and augment conflict analysis with a graphaware procedure. Our solution scales to graphs having millions of edges and vertices. It has been deployed at Intel for clock routing automation.

An Integrated Approach to a Combinatorial Optimisation Problem

“…Further justification for the adoption of SMT techniques is given by the fact that other authors also employ SAT or SMT solvers for simpler problems. SMT solvers are applied, in [11], to a particular optimal path selection problem in the semi-conductor manufacturing domain; besides the use of Bit-Vector capabilities of the SMT solver, there are little further similarities: the problem there can be described by only one graph, having one single cost annotation for each edge (we have multiple "costs" on each node). Work bearing some similarity with ours is in [19], presenting an graph-theoretical representation of a problem in computational task parallel scheduling, and also featuring a notion of temporal separation between nodes and of resources.…”

Scalable, high-quality, SAT-based multi-layer escape routing

“…Overall, work on escape routing fits into the broader topic of trace routing. There is a large body of work addressing PCB and VLSI wire routing [18,43,17], including several approaches applying constraint solvers: [7,6,8,4] applied SAT and answer-set-programming (ASP) solvers to rectilinear wire routing, and [9] applied an augmented SAT solver to clock routing. However, while these approaches are similar to ours in that they apply SAT solvers and related technologies to wire routing, none of them is appropriate for escape routing.…”